Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8856495 | Automatically routing super-compute interconnects | Wael R. El-Essawy, Jarrod A. Roy | 2014-10-07 |
| 8850163 | Automatically routing super-compute interconnects | Wael R. El-Essawy, Jarrod A. Roy | 2014-09-30 |
| 8725483 | Minimizing the maximum required link capacity for three-dimensional interconnect routing | Wael R. Ei-Essawy, Jarrod A. Roy | 2014-05-13 |
| 8677299 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-18 |
| 8667441 | Clock optimization with local clock buffer control optimization | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-04 |
| 8479136 | Decoupling capacitor insertion using hypergraph connectivity analysis | Jeremy T. Hopkins, Samuel I. Ward | 2013-07-02 |
| 8458634 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan | 2013-06-04 |
| 8418108 | Accuracy pin-slew mode for gate delay calculation | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan +1 more | 2013-04-09 |
| 8141017 | Method for bounded transactional timing analysis | Michael D. Moffitt | 2012-03-20 |
| 8015532 | Optimal timing-driven cloning under linear delay model | Charles J. Alpert, Zhuo Li, Chin Ngai Sze | 2011-09-06 |
| 7761832 | Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model | Charles J. Alpert, Zhuo Li, Tao Luo, Chin Ngai Sze | 2010-07-20 |
| 7707530 | Incremental timing-driven, physical-synthesis using discrete optimization | Charles J. Alpert, Zhuo Li, Michael D. Moffitt | 2010-04-27 |