Issued Patents All Time
Showing 51–75 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6040207 | Oxide formation technique using thin film silicon deposition | Mark I. Gardner | 2000-03-21 |
| 6027992 | Semiconductor device having a gallium and nitrogen containing barrier layer and method of manufacturing thereof | Mark I. Gardner | 2000-02-22 |
| 6027976 | Process for making semiconductor device having nitride at silicon and polysilicon interfaces | Mark I. Gardner | 2000-02-22 |
| 6005274 | Semiconductor device with a multi-level gate structure and a gate dielectric composed of barium zirconium titanate material | Mark I. Gardner | 1999-12-21 |
| 6004861 | Process for making a discontinuous source/drain formation for a high density integrated circuit | Mark I. Gardner | 1999-12-21 |
| 6002150 | Compound material T gate structure for devices with gate dielectrics having a high dielectric constant | Mark I. Gardner | 1999-12-14 |
| 5998270 | Formation of oxynitride and polysilicon layers in a single reaction chamber | Mark I. Gardner | 1999-12-07 |
| 5989967 | Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length | Mark I. Gardner | 1999-11-23 |
| 5990493 | Diamond etch stop rendered conductive by a gas cluster ion beam implant of titanium | Mark I. Gardner | 1999-11-23 |
| 5985706 | Polishing method for thin gates dielectric in semiconductor process | Mark I. Gardner | 1999-11-16 |
| 5976952 | Implanted isolation structure formation for high density CMOS integrated circuits | Mark I. Gardner | 1999-11-02 |
| 5963810 | Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-10-05 |
| 5943596 | Fabrication of a gate electrode stack using a patterned oxide layer | Mark I. Gardner | 1999-08-24 |
| 5940698 | Method of making a semiconductor device having high performance gate electrode structure | Mark I. Gardner | 1999-08-17 |
| 5937308 | Semiconductor trench isolation structure formed substantially within a single chamber | Mark I. Gardner | 1999-08-10 |
| 5930632 | Process of fabricating a semiconductor device having cobalt niobate gate electrode structure | Mark I. Gardner | 1999-07-27 |
| 5923949 | Semiconductor device having fluorine bearing sidewall spacers and method of manufacture thereof | Mark I. Gardner | 1999-07-13 |
| 5907780 | Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation | Mark I. Gardner | 1999-05-25 |
| 5904542 | Performing a semiconductor fabrication sequence within a common chamber and without opening the chamber beginning with forming a field dielectric and concluding with a gate dielectric | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-05-18 |
| 5897358 | Semiconductor device having fluorine-enhanced transistor with elevated active regions and fabrication thereof | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-04-27 |
| 5890269 | Semiconductor wafer, handling apparatus, and method | Mark I. Gardner | 1999-04-06 |
| 5888870 | Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate | Mark I. Gardner | 1999-03-30 |
| 5877057 | Method of forming ultra-thin oxides with low temperature oxidation | Mark I. Gardner | 1999-03-02 |
| 5872376 | Oxide formation technique using thin film silicon deposition | Mark I. Gardner | 1999-02-16 |
| 5858848 | Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate | Mark I. Gardner | 1999-01-12 |