Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6362526 | Alloy barrier layers for semiconductors | Shekhar Pramanick | 2002-03-26 |
| 6346472 | Manufacturing method for semiconductor metalization barrier | Sergey Lopatin | 2002-02-12 |
| 6344691 | Barrier materials for metal interconnect in a semiconductor device | Shekhar Pramanick | 2002-02-05 |
| 6340633 | Method for ramped current density plating of semiconductor vias and trenches | Sergey Lopatin | 2002-01-22 |
| 6320263 | Semiconductor metalization barrier and manufacturing method therefor | Sergey Lopatin | 2001-11-20 |
| 6261946 | Method for forming semiconductor seed layers by high bias deposition | Dirk Brown, Takeshi Nogami | 2001-07-17 |
| 6244210 | Strength coil for ionized copper plasma deposition | Paul R. Besser | 2001-06-12 |
| 6239021 | Dual barrier and conductor deposition in a dual damascene process for semiconductors | Shekhar Pramanick, Dirk Brown | 2001-05-29 |
| 6232230 | Semiconductor interconnect interface processing by high temperature deposition | — | 2001-05-15 |
| 6228754 | Method for forming semiconductor seed layers by inert gas sputter etching | Dirk Brown, Takeshi Nogami | 2001-05-08 |
| 6218078 | Creation of an etch hardmask by spin-on technique | — | 2001-04-17 |
| 6200913 | Cure process for manufacture of low dielectric constant interlevel dielectric layers | Lu You, Simon S. Chan, Richard J. Huang, Robin Cheung | 2001-03-13 |
| 6187670 | Multi-stage method for forming optimized semiconductor seed layers | Dirk Brown | 2001-02-13 |
| 6166427 | Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application | Richard J. Huang | 2000-12-26 |
| 6159851 | Borderless vias with CVD barrier layer | Robert Chen, David C. Greenlaw | 2000-12-12 |
| 6150268 | Barrier materials for metal interconnect | Shekhar Pramanick | 2000-11-21 |
| 6146993 | Method for forming in-situ implanted semiconductor barrier layers | Dirk Brown | 2000-11-14 |
| 6147404 | Dual barrier and conductor deposition in a dual damascene process for semiconductors | Shekhar Pramanick, Dirk Brown | 2000-11-14 |
| 6117770 | Method for implanting semiconductor conductive layers | Shekhar Pramanick, Dirk Brown, Christy Mei-Chu Woo | 2000-09-12 |
| 6110345 | Method and system for plating workpieces | — | 2000-08-29 |
| 6103085 | Electroplating uniformity by diffuser design | Christy Mei-Chu Woo, Kai Yang | 2000-08-15 |
| 6100181 | Low dielectric constant coating of conductive material in a damascene process for semiconductors | Lu You | 2000-08-08 |
| 6080669 | Semiconductor interconnect interface processing by high pressure deposition | Dirk Brown, Takeshi Nogami | 2000-06-27 |
| 6048790 | Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient | Eric N. Paton | 2000-04-11 |
| 5969425 | Borderless vias with CVD barrier layer | Robert Chen, David C. Greenlaw | 1999-10-19 |