Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12002869 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2024-06-04 |
| 11469309 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2022-10-11 |
| 10770388 | Transistor with recessed cross couple for gate contact over active region integration | Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Mahender Kumar +1 more | 2020-09-08 |
| 10714591 | Gate structure for a transistor device with a novel pillar structure positioned thereabove | Ruilong Xie, Hui Zang | 2020-07-14 |
| 10651284 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2020-05-12 |
| 10629701 | Self-aligned gate cut method and multilayer gate-cut pillar structure | Ruilong Xie, Hui Zang | 2020-04-21 |
| 10490455 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2019-11-26 |
| 10236215 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2019-03-19 |
| 10204861 | Structure with local contact for shorting a gate electrode to a source/drain region | Xuelian Zhu, Jia Zeng, Wenhui Wang, Jongwook Kye | 2019-02-12 |
| 10109636 | Active contact and gate contact interconnect for mitigating adjacent gate electrode shortages | Bipul C. Paul | 2018-10-23 |
| 9711511 | Vertical channel transistor-based semiconductor memory structure | Kwan-Yong Lim, Ryan Ryoung-Han Kim, Motoi Ichihashi, Deepak Nayak | 2017-07-18 |
| 9627389 | Methods to form merged spacers for use in fin generation in IC devices | Lei Yuan, Srinivasa Banna | 2017-04-18 |
| 9472464 | Methods to utilize merged spacers for use in fin generation in tapered IC devices | Jia Zeng, Lei Yuan, Yan Wang, Jongwook Kye | 2016-10-18 |
| 9466604 | Metal segments as landing pads and local interconnects in an IC device | Myungjun Lee, Ryan Ryoung-Han Kim, Jongwook Kye | 2016-10-11 |
| 9437481 | Self-aligned double patterning process for two dimensional patterns | Lei Yuan, Jia Zeng, Jongwook Kye | 2016-09-06 |
| 9406616 | Merged source/drain and gate contacts in SRAM bitcell | Ryan Ryoung-Han Kim | 2016-08-02 |
| 9406775 | Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints | Guillaume Bouche, Andy Wei | 2016-08-02 |
| 9324722 | Utilization of block-mask and cut-mask for forming metal routing in an IC device | Lei Yuan, Jongwook Kye | 2016-04-26 |
| 9268897 | Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devices | Lei Yuan, Hidekazu Yoshida, Jongwook Kye | 2016-02-23 |
| 9184169 | Methods of forming FinFET devices in different regions of an integrated circuit product | Ryan Ryoung-Han Kim | 2015-11-10 |
| 9105510 | Double sidewall image transfer process | Jongwook Kye, Dinesh Somasekhar | 2015-08-11 |
| 8962483 | Interconnection designs using sidewall image transfer (SIT) | Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye | 2015-02-24 |
| 8889561 | Double sidewall image transfer process | Jongwook Kye, Dinesh Somasekhar | 2014-11-18 |
| 7388262 | Nitrogen implementation to minimize device variation | Jae-Gyung Ahn | 2008-06-17 |