Issued Patents All Time
Showing 51–75 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11264274 | Reverse contact and silicide process for three-dimensional logic devices | Jeffrey Smith, Hiroaki Niimi, Jodi Grzeskowiak, Daniel Chanemougame, Kandabara Tapily +2 more | 2022-03-01 |
| 11251200 | Coaxial contacts for 3D logic and memory | Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily | 2022-02-15 |
| 11233006 | Metallization lines on integrated circuit products | Ruilong Xie, Daniel Chanemougame, Geng Han | 2022-01-25 |
| 11217583 | Architecture design of monolithically integrated 3D CMOS logic and memory | Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily | 2022-01-04 |
| 11201152 | Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor | Ruilong Xie, Steven R. Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier +1 more | 2021-12-14 |
| 11201148 | Architecture for monolithic 3D integration of semiconductor devices | Jeffrey Smith, Anton J. deVilliers | 2021-12-14 |
| 11177250 | Method for fabrication of high density logic and memory for advanced circuit architecture | Mark I. Gardner, H. Jim Fulford, Jeffrey Smith, Daniel Chanemougame | 2021-11-16 |
| 11114381 | Power distribution network for 3D logic and memory | Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily | 2021-09-07 |
| 11114346 | High density logic formation using multi-dimensional laser annealing | H. Jim Fulford, Mark I. Gardner, Jeffrey Smith, Daniel Chanemougame | 2021-09-07 |
| 11107733 | Multi-dimensional planes of logic and memory formation using single crystal silicon orientations | Mark I. Gardner, H. Jim Fulford, Jeffrey Smith, Daniel Chanemougame | 2021-08-31 |
| 11043418 | Middle of the line self-aligned direct pattern contacts | Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Gregory A. Northrop | 2021-06-22 |
| 10978388 | Skip via for metal interconnects | Hari Prasad Amanapu, Prasad Bhosale, Nicholas V. LiCausi, James Jay McMahon, Cornelius Brown Peethala +1 more | 2021-04-13 |
| 10916478 | Methods of performing fin cut etch processes for FinFET semiconductor devices | Lei Zhuang, Balasubramanian Pranatharthiharan, Ruilong Xie, Terence B. Hook | 2021-02-09 |
| 10879375 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2020-12-29 |
| 10872809 | Contact structures for integrated circuit products | Ruilong Xie, Balasubramanian S. Pranatharthi Haran, Veeraraghavan S. Basker | 2020-12-22 |
| 10796056 | Optimizing library cells with wiring in metallization layers | Gregory A. Northrop, Lionel Riviere-Cazaux, Kai Sun, Norihito Nakamoto | 2020-10-06 |
| 10727308 | Gate contact structure for a transistor | Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Mark V. Raymond | 2020-07-28 |
| 10720391 | Method of forming a buried interconnect and the resulting devices | Bipul C. Paul, Ruilong Xie | 2020-07-21 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven R. Soss, Hui Zang +1 more | 2020-06-30 |
| 10685874 | Self-aligned cuts in an interconnect structure | Ruilong Xie, Hui Zang, Lei Sun, Daniel Chanemougame, Guillaume Bouche | 2020-06-16 |
| 10651284 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Heimanu Niebojewski +3 more | 2020-05-12 |
| 10586762 | Interrupted small block shape | Guillaume Bouche | 2020-03-10 |
| 10522403 | Middle of the line self-aligned direct pattern contacts | Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Gregory A. Northrop | 2019-12-31 |
| 10522654 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2019-12-31 |
| 10504790 | Methods of forming conductive spacers for gate contacts and the resulting device | Ruilong Xie, Bipul C. Paul, Daniel Chanemougame, Nigel G. Cave | 2019-12-10 |