Issued Patents All Time
Showing 26–50 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11735525 | Power delivery network for CFET with buried power rails | Jeffrey Smith, Anton J. deVilliers, Daniel Chanemougame | 2023-08-22 |
| 11723187 | Three-dimensional memory cell structure | Paul Gutwin, Daniel Chanemougame | 2023-08-08 |
| 11714945 | Method for automated standard cell design | — | 2023-08-01 |
| 11676968 | Coaxial contacts for 3D logic and memory | Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily | 2023-06-13 |
| 11665878 | CFET SRAM bit cell with two stacked device decks | Daniel Chanemougame, Jeffrey Smith | 2023-05-30 |
| 11646318 | Connections from buried interconnects to device terminals in multiple stacked devices structures | Daniel Chanemougame, Jeffrey Smith | 2023-05-09 |
| 11631671 | 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same | H. Jim Fulford, Anton J. deVilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith +1 more | 2023-04-18 |
| 11621333 | Gate contact structure for a transistor device | Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Mark V. Raymond | 2023-04-04 |
| 11616020 | Power distribution network for 3D logic and memory | Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily | 2023-03-28 |
| 11581242 | Integrated high efficiency gate on gate cooling | Daniel Chanemougame, Jeffrey Smith, Paul Gutwin | 2023-02-14 |
| 11574845 | Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices | Daniel Chanemougame, Jeffrey Smith, Anton J. deVilliers | 2023-02-07 |
| 11550985 | Method for automated standard cell design | — | 2023-01-10 |
| 11545497 | CFET SRAM bit cell with three stacked device decks | Daniel Chanemougame, Jeffrey Smith | 2023-01-03 |
| 11532708 | Stacked three-dimensional field-effect transistors | Jeffrey Smith, Daniel Chanemougame, Paul Gutwin | 2022-12-20 |
| 11495540 | Semiconductor apparatus having stacked devices and method of manufacture thereof | Jeffrey Smith, Anton J. deVilliers | 2022-11-08 |
| 11488947 | Highly regular logic design for efficient 3D integration | Jeffrey Smith, Daniel Chanemougame, Anton J. deVilliers | 2022-11-01 |
| 11469146 | Methods of performing fin cut etch processes for FinFET semiconductor devices | Lei Zhuang, Balasubramanian Pranatharthiharan, Ruilong Xie, Terence B. Hook | 2022-10-11 |
| 11469309 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Heimanu Niebojewski +3 more | 2022-10-11 |
| 11450671 | Semiconductor apparatus having stacked devices and method of manufacture thereof | Jeffrey Smith, Anton J. deVilliers, Daniel Chanemougame | 2022-09-20 |
| 11437376 | Compact 3D stacked-CFET architecture for complex logic cells | Jeffrey Smith, Anton J. deVilliers, Daniel Chanemougame | 2022-09-06 |
| 11342427 | 3D directed self-assembly for nanostructures | Anton J. deVilliers, Jodi Grzeskowiak, Daniel Chanemougame | 2022-05-24 |
| 11335599 | Self-aligned contacts for 3D logic and memory | Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily | 2022-05-17 |
| 11322401 | Reverse contact and silicide process for three-dimensional semiconductor devices | Jeffrey Smith, Daniel Chanemougame, Hiroki Niimi, Kandabara Tapily, Subhadeep Kal +2 more | 2022-05-03 |
| 11309210 | Self aligned buried power rail | Nicholas V. LiCausi, Guillaume Bouche | 2022-04-19 |
| 11264289 | Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks | Jeffrey Smith, Kandabara Tapily, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more | 2022-03-01 |