Issued Patents All Time
Showing 25 most recent of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12237328 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek | 2025-02-25 |
| 12237368 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2025-02-25 |
| 11664375 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek | 2023-05-30 |
| 11038055 | Method and structure of improving contact resistance for passive and long channel devices | Injo Ok, Soon-Cheon Seo, Balasubramanian Pranatharthiharan | 2021-06-15 |
| 11037875 | Forming dual metallization interconnect structures in single metallization level | Hari Prasad Amanapu, Raghuveer R. Patlolla | 2021-06-15 |
| 11031337 | Forming dual metallization interconnect structures in single metallization level | Hari Prasad Amanapu, Raghuveer R. Patlolla | 2021-06-08 |
| 11011429 | Minimize middle-of-line contact line shorts | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2021-05-18 |
| 10896816 | Silicon residue removal in nanosheet transistors | Zhenxing Bi, Thamarai S. Devarajan, Nicolas Loubet, Binglin Miao, Muthumanickam Sankarapandian +2 more | 2021-01-19 |
| 10804159 | Minimize middle-of-line contact line shorts | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2020-10-13 |
| 10629721 | Contact resistance reduction for advanced technology nodes | Injo Ok, Balasubramanian Pranatharthiharan | 2020-04-21 |
| 10559654 | Nanosheet isolation for bulk CMOS non-planar devices | Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo | 2020-02-11 |
| 10559530 | Forming dual metallization interconnect structures in single metallization level | Hari Prasad Amanapu, Raghuveer R. Patlolla | 2020-02-11 |
| 10490454 | Minimize middle-of-line contact line shorts | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2019-11-26 |
| 10396200 | Method and structure of improving contact resistance for passive and long channel devices | Injo Ok, Soon-Cheon Seo, Balasubramanian Pranatharthiharan | 2019-08-27 |
| 10381458 | Semiconductor device replacement metal gate with gate cut last in RMG | Andrew M. Greene, Balasubramanian Pranatharthi Haran, Injo Ok | 2019-08-13 |
| 10361203 | FET trench dipole formation | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2019-07-23 |
| 10355080 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2019-07-16 |
| 10347633 | Spacer for trench epitaxial structures | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2019-07-09 |
| 10347632 | Forming spacer for trench epitaxial structures | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2019-07-09 |
| 10347628 | Simultaneously fabricating a high voltage transistor and a FinFET | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2019-07-09 |
| 10276569 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek | 2019-04-30 |
| 10256296 | Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2019-04-09 |
| 10249624 | Semiconductor structure containing low-resistance source and drain contacts | Injo Ok, Balasubramanian Pranatharthiharan | 2019-04-02 |
| 10243044 | FinFETs with high quality source/drain structures | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2019-03-26 |
| 10229852 | Self-aligned low dielectric constant gate cap and a method of forming the same | Balasubramanian Pranatharthiharan, Injo Ok | 2019-03-12 |