Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10204828 | Enabling low resistance gates and contacts integrated with bilayer dielectrics | Ruqiang Bao, Benjamin D. Briggs, Lawrence A. Clevenger, Koichi Motoyama, Cornelius Brown Peethala +1 more | 2019-02-12 |
| 10170477 | Forming MOSFET structures with work function modification | Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Reinaldo Vega +1 more | 2019-01-01 |
| 10147725 | Forming MOSFET structures with work function modification | Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Reinaldo Vega +1 more | 2018-12-04 |
| 10115728 | Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trench | Zuoguang Liu, Heng Wu, Peng Xu | 2018-10-30 |
| 10096713 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Chun-Chen Yeh | 2018-10-09 |
| 10032679 | Self-aligned doping in source/drain regions for low contact resistance | Dechao Guo, Zuoguang Liu, Heng Wu | 2018-07-24 |
| 9812556 | Semiconductor device and method of manufacturing the semiconductor device | Shogo Mochizuki, Raghavasimhan Sreenivasan, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek | 2017-11-07 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Kangguo Cheng, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy +6 more | 2017-08-01 |
| 8604546 | Reducing gate resistance in nonplanar multi-gate transistor | Andres Bryant, Theodorus E. Standaert, Chun-Chen Yeh | 2013-12-10 |
| 8586437 | Semiconductor device and method of manufacturing the semiconductor device | Toshiyuki Iwamoto | 2013-11-19 |
| 8269271 | Hybrid planarFET and FinFET provided on a chip | Toshiyuki Iwamoto | 2012-09-18 |
| 8088677 | Method of manufacturing semiconductor device, and semiconductor device | — | 2012-01-03 |