Issued Patents All Time
Showing 26–50 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11710521 | Static random-access memory cell design | Lan Yu, Junli Wang, Heng Wu, Ruqiang Bao | 2023-07-25 |
| 11688635 | Oxygen-free replacement liner for improved transistor performance | Heng Wu, Junli Wang, Ruqiang Bao | 2023-06-27 |
| 11665877 | Stacked FET SRAM design | Chen Zhang, Ruilong Xie, Junli Wang | 2023-05-30 |
| 11658116 | Interconnects on multiple sides of a semiconductor structure | Junli Wang, Albert M. Chu, Brent A. Anderson | 2023-05-23 |
| 11652156 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Carl Radens, Kangguo Cheng, Juntao Li, Tao Li +1 more | 2023-05-16 |
| 11456219 | Gate-all-around FETs having uniform threshold voltage | Ruqiang Bao, Junli Wang, Heng Wu | 2022-09-27 |
| 11289573 | Contact resistance reduction in nanosheet device structure | Heng Wu, Ruqiang Bao, Junli Wang, Lan Yu, Reinaldo Vega +1 more | 2022-03-29 |
| 11282838 | Stacked gate structures | Chen Zhang, Junli Wang, Ruilong Xie, Kangguo Cheng, Juntao Li +5 more | 2022-03-22 |
| 11282186 | Anomaly detection using image-based physical characterization | Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou | 2022-03-22 |
| 11251288 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Carl Radens, Kangguo Cheng, Juntao Li, Tao Li +1 more | 2022-02-15 |
| 11201153 | Stacked field effect transistor with wrap-around contacts | Ruilong Xie, Chun-Chen Yeh, Alexander Reznicek | 2021-12-14 |
| 11189729 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2021-11-30 |
| 11164782 | Self-aligned gate contact compatible cross couple contact formation | Ruilong Xie, Balasubramanian S. Pranatharthi Haran, Nicolas Loubet, Alexander Reznicek | 2021-11-02 |
| 11094824 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2021-08-17 |
| 11069684 | Stacked field effect transistors with reduced coupling effect | Ruilong Xie, Chun-Chen Yeh, Alexander Reznicek | 2021-07-20 |
| 11024369 | Static random-access memory cell design | Lan Yu, Junli Wang, Heng Wu, Ruqiang Bao | 2021-06-01 |
| 11011517 | Semiconductor structure including first FinFET devices for low power applications and second FinFET devices for high power applications | Lan Yu, Junli Wang, Heng Wu, Ruqiang Bao | 2021-05-18 |
| 10971626 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki +3 more | 2021-04-06 |
| 10971399 | Oxygen-free replacement liner for improved transistor performance | Heng Wu, Junli Wang, Ruqiang Bao | 2021-04-06 |
| 10957696 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Brent A. Anderson, Ruqiang Bao, Vijay Narayanan | 2021-03-23 |
| 10943989 | Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization | Heng Wu, Ruqiang Bao, Junli Wang, Lan Yu | 2021-03-09 |
| 10937648 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Ruqiang Bao, Gen Tsutsui | 2021-03-02 |
| 10892181 | Semiconductor device with mitigated local layout effects | Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Huiming Bu +1 more | 2021-01-12 |
| 10840345 | Source and drain contact cut last process to enable wrap-around-contact | Andrew M. Greene, Tenko Yamashita, Veeraraghavan S. Basker, Robert R. Robison, Ardasheir Rahman | 2020-11-17 |
| 10804368 | Semiconductor device having two-part spacer | Ruqiang Bao, Junli Wang, Heng Wu, Ernest Y. Wu | 2020-10-13 |