Issued Patents All Time
Showing 76–100 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10211207 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Praneet Adusumilli, Oleg Gluschenkov, Zuoguang Liu, Rajasekhar Venigalla, Tenko Yamashita | 2019-02-19 |
| 10170593 | Threshold voltage modulation through channel length adjustment | Ruqiang Bao, Derrick Liu, Huimei Zhou | 2019-01-01 |
| 10170368 | Fabricating fin-based split-gate high-drain-voltage transistor by work function tuning | Liyang Song, Xinhui Wang, Qintao Zhang | 2019-01-01 |
| 10141308 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Praneet Adusumilli, Oleg Gluschenkov, Zuoguang Liu, Rajasekhar Venigalla, Tenko Yamashita | 2018-11-27 |
| 10128239 | Preserving channel strain in fin cuts | Andrew M. Greene, Ravikumar Ramachandran, Rajasekhar Venigalla | 2018-11-13 |
| 10096713 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh | 2018-10-09 |
| 10068805 | Self-aligned spacer for cut-last transistor fabrication | Ruqiang Bao, Zuoguang Liu | 2018-09-04 |
| 10056382 | Modulating transistor performance | Juntao Li, Sanjay C. Mehta, Robert R. Robison, Huimei Zhou | 2018-08-21 |
| 10056378 | Silicon nitride fill for PC gap regions to increase cell density | Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2018-08-21 |
| 10043891 | Replacement metal gate scheme with self-alignment gate for vertical field effect transistors | Raqiang Bao | 2018-08-07 |
| 10032679 | Self-aligned doping in source/drain regions for low contact resistance | Zuoguang Liu, Gen Tsutsui, Heng Wu | 2018-07-24 |
| 10020378 | Self-aligned spacer for cut-last transistor fabrication | Ruqiang Bao, Zuoguang Liu | 2018-07-10 |
| 9978750 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Praneet Adusumilli, Oleg Gluschenkov, Zuoguang Liu, Rajasekhar Venigalla, Tenko Yamashita | 2018-05-22 |
| 9960254 | Replacement metal gate scheme with self-alignment gate for vertical field effect transistors | Raqiang Bao | 2018-05-01 |
| 9941282 | Integrated metal gate CMOS devices | Ruqiang Bao, Vijay Narayanan | 2018-04-10 |
| 9922984 | Threshold voltage modulation through channel length adjustment | Ruqiang Bao, Derrick Liu, Huimei Zhou | 2018-03-20 |
| 9922983 | Threshold voltage modulation through channel length adjustment | Ruqiang Bao, Derrick Liu, Huimei Zhou | 2018-03-20 |
| 9899264 | Integrated metal gate CMOS devices | Ruqiang Bao, Vijay Narayanan | 2018-02-20 |
| 9859286 | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2018-01-02 |
| 9859275 | Silicon nitride fill for PC gap regions to increase cell density | Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2018-01-02 |
| 9853116 | Partial sacrificial dummy gate with CMOS device with high-k metal gate | Wilfried E. Haensch, Shu-Jen Han, Daniel Jaeger, Yu Lu, Keith Kwong Hon Wong | 2017-12-26 |
| 9793272 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage | Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh | 2017-10-17 |
| 9786661 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh | 2017-10-10 |
| 9773893 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2017-09-26 |
| 9768027 | FinFET having controlled dielectric region height | Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2017-09-19 |