Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8785981 | Non-replacement gate nanomesh field effect transistor with pad regions | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2014-07-22 |
| 8778768 | Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain | Josephine B. Chang, Issac Lauer, Jeffrey W. Sleight | 2014-07-15 |
| 8779414 | Collapsable gate for deposited nanostructures | Josephine B. Chang, Michael A. Guillorn, Philip S. Waggoner | 2014-07-15 |
| 8754403 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels | Josephine B. Chang, Vijay Narayanan, Jeffrey W. Sleight | 2014-06-17 |
| 8741722 | Formation of dividers between gate ends of field effect transistor devices | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2014-06-03 |
| 8703576 | Gap-fill keyhole repair using printable dielectric material | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2014-04-22 |
| 8652916 | Self aligned impact-ionization MOS (I-MOS) device and methods of manufacture | Roger A. Booth, Jr., Kangguo Cheng, Chengwen Pei, William R. Tonti | 2014-02-18 |
| 8637371 | Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same | Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight | 2014-01-28 |
| 8626480 | Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors | Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park +2 more | 2014-01-07 |
| 8586449 | Raised isolation structure self-aligned to fin structures | Josephine B. Chang, Michael A. Guillorn, Effendi Leobandung | 2013-11-19 |
| 8557648 | Recessed source and drain regions for FinFETs | Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-10-15 |
| 8554282 | Methods, devices and computer program products for presenting screen content | — | 2013-10-08 |
| 8513099 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels | Josephine B. Chang, Vijay Narayanan, Jeffrey W. Sleight | 2013-08-20 |
| 8492748 | Collapsable gate for deposited nanostructures | Josephine B. Chang, Michael A. Guillorn, Philip S. Waggoner | 2013-07-23 |
| 8472239 | Nanowire mesh FET with multiple threshold voltages | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2013-06-25 |
| 8466451 | Single gate inverter nanowire mesh | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2013-06-18 |
| 8422273 | Nanowire mesh FET with multiple threshold voltages | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2013-04-16 |
| 8395220 | Nanomesh SRAM cell | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2013-03-12 |
| 8216902 | Nanomesh SRAM cell | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2012-07-10 |
| 8084308 | Single gate inverter nanowire mesh | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2011-12-27 |
| 7964933 | Integrated circuit including power diode | Geeng-Chuan Chern, Prognyan Ghosh, Wayne Y. W. Hsueh, Vladimir Rodov | 2011-06-21 |
| 7893492 | Nanowire mesh device and method of fabricating same | Stephen W. Bedell, Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2011-02-22 |
| 7892945 | Nanowire mesh device and method of fabricating same | Stephen W. Bedell, Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2011-02-22 |
| 7709910 | Semiconductor structure for low parasitic gate capacitance | William K. Henson, Dureseti Chidambarrao, Ricardo A. Donaton, Yaocheng Liu, Shreesh Narasimha +1 more | 2010-05-04 |
| 7554523 | Peripheral device for image display apparatus | Yu-Chi Lin | 2009-06-30 |