Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7749830 | CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETS | Bruce B. Doris, William K. Henson, Richard S. Wise | 2010-07-06 |
| 7691701 | Method of forming gate stack and structure thereof | Michael P. Belyansky, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Ravikumar Ramachandran +3 more | 2010-04-06 |
| 7671421 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-Yung Sung +2 more | 2010-03-02 |
| 7438822 | Apparatus and method for shielding a wafer from charged particles during plasma etching | Brian L. Ji, Siddhartha Panda, Richard S. Wise, Bomy Chen | 2008-10-21 |
| 7435652 | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET | Tze-Chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Qingyun Yang, Ying Zhang | 2008-10-14 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance | Richard S. Wise, Bomy Chen, Mark C. Hakey | 2008-02-12 |
| 7081393 | Reduced dielectric constant spacer materials integration for high speed logic gates | Michael P. Belyansky, Joyce C. Liu, Hsing-Jen Wann, Richard S. Wise | 2006-07-25 |
| 7077903 | Etch selectivity enhancement for tunable etch resistant anti-reflective layer | Katherina Babich, Scott D. Halle, David V. Horak, Arpan Mahorowala, Wesley C. Natzle +1 more | 2006-07-18 |
| 6908806 | Gate metal recess for oxidation protection and parasitic capacitance reduction | Haining Yang, Ramachandra Divakaruni, Oleg Gluschenkov, Rajeev Malik, Ravikumar Ramachandran | 2005-06-21 |
| 6838347 | Method for reducing line edge roughness of oxide material using chemical oxide removal | Joyce C. Liu, Wesley C. Natzle, Richard S. Wise, Bidan Zhang | 2005-01-04 |
| 6541320 | Method to controllably form notched polysilicon gate structures | Jeffrey J. Brown, Richard S. Wise, Qingyun Yang, Chienfan Yu | 2003-04-01 |
| 6509219 | Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch | Len Yuan Tsou, Qingyun Yang, Chienfan Yu | 2003-01-21 |
| 6345399 | Hard mask process to prevent surface roughness for selective dielectric etching | Paul C. Jamison, Tina Wagner, Richard S. Wise | 2002-02-12 |
| 6294102 | Selective dry etch of a dielectric film | Delores Bennett, James P. Norum, Chienfan Yu | 2001-09-25 |