Issued Patents All Time
Showing 26–50 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9793398 | Fabrication of a strained region on a substrate | Isaac Lauer, Jiaxing Liu | 2017-10-17 |
| 9773903 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Yanning Sun | 2017-09-26 |
| 9768195 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2017-09-19 |
| 9739728 | Automatic defect detection and classification for high throughput electron channeling contrast imaging | Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser | 2017-08-22 |
| 9698239 | Growing groups III-V lateral nanowire channels | Sanghoon Lee, Effendi Leobandung, Brent A. Wacaser | 2017-07-04 |
| 9698159 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2017-07-04 |
| 9680018 | Method of forming high-germanium content silicon germanium alloy fins on insulator | Pouya Hashemi, John A. Ott, Alexander Reznicek | 2017-06-13 |
| 9659961 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2017-05-23 |
| 9627266 | Dual-semiconductor complementary metal-oxide-semiconductor device | Sanghoon Lee, Effendi Leobandung, Yanning Sun | 2017-04-18 |
| 9627271 | III-V compound semiconductor channel material formation on mandrel after middle-of-the-line dielectric formation | Effendi Leobandung | 2017-04-18 |
| 9553166 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Yanning Sun | 2017-01-24 |
| 9536985 | Epitaxial growth of material on source/drain regions of FinFET structure | Michael P. Chudzik, Brian J. Greene, Eric C. Harley, Judson R. Holt, Yue Ke +2 more | 2017-01-03 |
| 9437614 | Dual-semiconductor complementary metal-oxide-semiconductor device | Sanghoon Lee, Effendi Leobandung, Yanning Sun | 2016-09-06 |
| 9425079 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2016-08-23 |
| 9401325 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2016-07-26 |
| 9263276 | High-k/metal gate transistor with L-shaped gate encapsulation layer | Wesley C. Natzle, Vijay Narayanan, Jeffrey W. Sleight | 2016-02-16 |
| 9252018 | High-k/metal gate transistor with L-shaped gate encapsulation layer | Wesley C. Natzle, Vijay Narayanan, Jeffrey W. Sleight | 2016-02-02 |
| 9219059 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2015-12-22 |
| 9059316 | Structure and method for mobility enhanced MOSFETs with unalloyed silicide | Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Kern Rim | 2015-06-16 |
| 8878298 | Multiple Vt field-effect transistor devices | Josephine B. Chang, Leland Chang, Vijay Narayanan, Jeffrey W. Sleight | 2014-11-04 |
| 8816473 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Arvind Kumar, Anthony I. Chou, Shreesh Narasimha | 2014-08-26 |
| 8766259 | Test structure for detection of gap in conductive layer of multilayer gate stack | Oliver D. Patterson, Xing Zhou | 2014-07-01 |
| 8667448 | Integrated circuit having local maximum operating voltage | Anthony I. Chou, Arvind Kumar | 2014-03-04 |
| 8642434 | Structure and method for mobility enhanced MOSFETS with unalloyed silicide | Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Kern Rim | 2014-02-04 |
| 8507992 | High-K metal gate CMOS | Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan | 2013-08-13 |