Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10937871 | III-V transistor device with self-aligned doped bottom barrier | Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar | 2021-03-02 |
| 10622207 | Low external resistance channels in III-V semiconductor devices | Effendi Leobandung | 2020-04-14 |
| 10128343 | III-V MOSFET with self-aligned diffusion barrier | Kevin K. Chan, Cheng-Wei Cheng, Jack O. Chu, Jeng-Bang Yau | 2018-11-13 |
| 10115833 | Self-aligned heterojunction field effect transistor | Bahman Hekmatshoartabari, Ghavam G. Shahidi | 2018-10-30 |
| 10014377 | III-V field effect transistor on a dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu | 2018-07-03 |
| 9984873 | Preparation of low defect density of III-V on Si for device fabrication | Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu | 2018-05-29 |
| 9947755 | III-V MOSFET with self-aligned diffusion barrier | Kevin K. Chan, Cheng-Wei Cheng, Jack O. Chu, Jeng-Bang Yau | 2018-04-17 |
| 9941363 | III-V transistor device with self-aligned doped bottom barrier | Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar | 2018-04-10 |
| 9882021 | Planar III-V field effect transistor (FET) on dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana +1 more | 2018-01-30 |
| 9853109 | III-V MOSFET with self-aligned diffusion barrier | Kevin K. Chan, Cheng-Wei Cheng, Jack O. Chu, Jeng-Bang Yau | 2017-12-26 |
| 9812323 | Low external resistance channels in III-V semiconductor devices | Effendi Leobandung | 2017-11-07 |
| 9793405 | Semiconductor lateral sidewall growth from a semiconductor pillar | Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung, Renee T. Mo | 2017-10-17 |
| 9773903 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo | 2017-09-26 |
| 9741871 | Self-aligned heterojunction field effect transistor | Bahman Hekmatshoartabari, Ghavam G. Shahidi | 2017-08-22 |
| 9722031 | Reduced current leakage semiconductor device | Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung | 2017-08-01 |
| 9711648 | Structure and method for CMP-free III-V isolation | Effendi Leobandung, Chung-Hsun Lin, Amlan Majumdar | 2017-07-18 |
| 9704958 | III-V field effect transistor on a dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu | 2017-07-11 |
| 9666684 | III-V semiconductor device having self-aligned contacts | Anirban Basu, Amlan Majumdar | 2017-05-30 |
| 9627266 | Dual-semiconductor complementary metal-oxide-semiconductor device | Sanghoon Lee, Effendi Leobandung, Renee T. Mo | 2017-04-18 |
| 9627482 | Reduced current leakage semiconductor device | Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung | 2017-04-18 |
| 9608066 | High-K spacer for extension-free CMOS devices with high mobility channel materials | Takashi Ando, Pouya Hashemi, Vijay Narayanan | 2017-03-28 |
| 9570296 | Preparation of low defect density of III-V on Si for device fabrication | Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu | 2017-02-14 |
| 9553166 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo | 2017-01-24 |
| 9508640 | Multiple via structure and method | Cheng-Wei Cheng, Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Amlan Majumdar +2 more | 2016-11-29 |
| 9508550 | Preparation of low defect density of III-V on Si for device fabrication | Cheng-Wei Cheng, Devendra K. Sadana, Keun-Ting Shiu | 2016-11-29 |