Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
RM

Renee T. Mo

IBM: 96 patents #604 of 70,183Top 1%
FSFreeescale Semiconductor: 1 patents #2,021 of 3,767Top 55%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
Yorktown Heights, NY: #24 of 858 inventorsTop 3%
New York: #569 of 115,490 inventorsTop 1%
Overall (All Time): #15,177 of 4,157,543Top 1%
98 Patents All Time

Issued Patents All Time

Showing 76–98 of 98 patents

Patent #TitleCo-InventorsDate
7776732 Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same Leland Chang, Isaac Lauer, Jeffrey W. Sleight 2010-08-17
7767579 Protection of SiGe during etch and clean operations Ashima B. Chakravarti, Zhijiong Luo, Shreesh Narasimha, Katsunori Onishi 2010-08-03
7754594 Method for tuning the threshold voltage of a metal gate and high-k device Michael P. Chudzik, Michael A. Gribelyuk, Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong 2010-07-13
7652332 Extremely-thin silicon-on-insulator transistor with raised source/drain Eduard A. Cartier, Steven J. Koester, Kingsuk Maitra, Amlan Majumdar 2010-01-26
7648868 Metal-gated MOSFET devices having scaled gate stack thickness Amlan Majumdar, Zhibin Ren, Jeffrey W. Sleight 2010-01-19
7618891 Method for forming self-aligned metal silicide contacts Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Balasubramanian Pranatharthiharan +1 more 2009-11-17
7611979 Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Vijay Narayanan, Dae-Gyu Park +2 more 2009-11-03
7544610 Method and process for forming a self-aligned silicide contact Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr +5 more 2009-06-09
7518145 Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same Anthony I. Chou, Shreesh Narasimha 2009-04-14
7498271 Nitrogen based plasma process for metal gate MOS device Ricardo A. Donaton, Rashmi Jha, Siddarth A. Krishnan, Xi Li, Naim Moumen +3 more 2009-03-03
7491964 Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process Fred Buehrer, Anthony I. Chou, Toshiharu Furukawa 2009-02-17
7491563 Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process Fred Buehrer, Anthony I. Chou, Toshiharu Furukawa 2009-02-17
7446005 Manufacturable recessed strained RSD structure and process for advanced CMOS Brian W. Messenger, Dominic J. Schepis 2008-11-04
7358130 Method for monitoring lateral encroachment of spacer process on a CD SEM Bachir Dirahoui, Ravikumar Ramachandran, Eric P. Solecky 2008-04-15
7344983 Clustered surface preparation for silicide and metal contacts Sadanand V. Deshpande, Ying Li, Kevin E. Mello, Wesley C. Natzle, Kirk D. Peterson +1 more 2008-03-18
7115955 Semiconductor device having a strained raised source/drain Brian W. Messenger, Dominic J. Schepis 2006-10-03
7105398 Method for monitoring lateral encroachment of spacer process on a CD SEM Bachir Dirahoui, Ravikumar Ramachandran, Eric P. Solecky 2006-09-12
7091128 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs Atul Ajmera, Andres Bryant, Percy V. Gilbert, Michael A. Gribelyuk, Edward P. Maciejewski +1 more 2006-08-15
7071103 Chemical treatment to retard diffusion in a semiconductor overlayer Kevin K. Chan, Huajie Chen, Michael A. Gribelyuk, Judson R. Holt, Woo-Hyeong Lee +5 more 2006-07-04
7071072 Forming shallow trench isolation without the use of CMP Shreesh Narasimha 2006-07-04
7002214 Ultra-thin body super-steep retrograde well (SSRW) FET devices Diane C. Boyd, Judson R. Holt, Meikei Ieong, Zhibin Ren, Ghavam G. Shahidi 2006-02-21
6991979 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs Atul Ajmera, Andres Bryant, Percy V. Gilbert, Michael A. Gribelyuk, Edward P. Maciejewski +1 more 2006-01-31
6790733 Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer Wesley C. Natzle, Bruce B. Doris, Sadanand V. Deshpande, Patricia A. O'Neil 2004-09-14