Issued Patents All Time
Showing 126–150 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8901616 | Gate stack including a high-K gate dielectric that is optimized for low voltage applications | Martin M. Frank, Jeffrey W. Sleight | 2014-12-02 |
| 8877593 | Semiconductor device including an asymmetric feature, and method of making the same | Josephine B. Chang, Chung-Hsun Lin, Jeffrey Sleight | 2014-11-04 |
| 8872274 | Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain | Guy M. Cohen, David J. Frank | 2014-10-28 |
| 8872241 | Multi-direction wiring for replacement gate lines | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2014-10-28 |
| 8865531 | Multi-direction wiring for replacement gate lines | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2014-10-21 |
| 8859410 | Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications | Martin M. Frank, Jeffrey W. Sleight | 2014-10-14 |
| 8853790 | Semiconductor nanowire structure reusing suspension pads | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2014-10-07 |
| 8823064 | Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2014-09-02 |
| 8822278 | Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2014-09-02 |
| 8816327 | Nanowire efuses | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2014-08-26 |
| 8809131 | Replacement gate fin first wire last gate all around devices | Sarunya Bangsaruntip, Josephine B. Chang, Jeffrey W. Sleight | 2014-08-19 |
| 8802527 | Gate electrode optimized for low voltage operation | Martin M. Frank, Jeffrey W. Sleight | 2014-08-12 |
| 8796735 | Fabrication of a vertical heterojunction tunnel-FET | Amlan Majumdar, Paul M. Solomon, Steven J. Koester | 2014-08-05 |
| 8796742 | Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain | Josephine B. Chang, Paul Chang, Jeffrey W. Sleight | 2014-08-05 |
| 8785981 | Non-replacement gate nanomesh field effect transistor with pad regions | Josephine B. Chang, Paul Chang, Jeffrey W. Sleight | 2014-07-22 |
| 8778759 | Gate electrode optimized for low voltage operation | Martin M. Frank, Jeffrey W. Sleight | 2014-07-15 |
| 8766353 | Tunnel field effect transistor | Bruce B. Doris, Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Ghavam G. Shahidi | 2014-07-01 |
| 8754530 | Self-aligned borderless contacts for high density electronic and memory device integration | Katherina Babich, Josephine B. Chang, Nicholas C. M. Fuller, Michael A. Guillorn, Michael J. Rooks | 2014-06-17 |
| 8723162 | Nanowire tunnel field effect transistors | Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight | 2014-05-13 |
| 8716091 | Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain | Guy M. Cohen, David J. Frank | 2014-05-06 |
| 8716798 | Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors | Nicholas C. M. Fuller, Steve Koester, Ying Zhang | 2014-05-06 |
| 8698128 | Gate-all around semiconductor nanowire FET's on bulk semicoductor wafers | Jeffrey W. Sleight, Josephine B. Chang, Shreesh Narasimha | 2014-04-15 |
| 8686506 | High performance devices and high density devices on single chip | Leland Chang, Jeffrey W. Sleight | 2014-04-01 |
| 8673731 | Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2014-03-18 |
| 8674342 | Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers | Jeffrey W. Sleight, Josephine B. Chang, Shreesh Narasimha | 2014-03-18 |