Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10083880 | Hybrid ETSOI structure to minimize noise coupling from TSV | Chung-Hsun Lin, Shih-Hsien Lo, Joel A. Silberman | 2018-09-25 |
| 9715437 | Pulsed-latch based razor with 1-cycle error recovery scheme | Jae-Joon Kim, Insup Shin | 2017-07-25 |
| 9653615 | Hybrid ETSOI structure to minimize noise coupling from TSV | Chung-Hsun Lin, Shih-Hsien Lo, Joel A. Silberman | 2017-05-16 |
| 9292390 | Pulsed-latch based razor with 1-cycle error recovery scheme | Jae-Joon Kim, Insup Shin | 2016-03-22 |
| 9087909 | Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSV | Chung-Hsun Lin, Shih-Hsien Lo, Joel A. Silberman | 2015-07-21 |
| 9009545 | Pulsed-latch based razor with 1-cycle error recovery scheme | Jae-Joon Kim, Insup Shin | 2015-04-14 |
| 8824282 | Network simulation and analysis using operational forwarding data | Pradeep Singh, Vinod Jeyachandran | 2014-09-02 |
| 8587357 | AC supply noise reduction in a 3D stack with voltage sensing and clock shifting | Jae-Joon Kim, Liang Pang, Joel A. Silberman | 2013-11-19 |
| 8576000 | 3D chip stack skew reduction with resonant clock and inductive coupling | Jae-Joon Kim, Liang Pang, Joel A. Silberman | 2013-11-05 |
| 8466739 | 3D chip stack skew reduction with resonant clock and inductive coupling | Jae-Joon Kim, Liang Pang, Joel A. Silberman | 2013-06-18 |
| 7189640 | Method of forming damascene structures | Chun-Jen Weng, Chih-Yi Cheng | 2007-03-13 |