Issued Patents All Time
Showing 25 most recent of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497711 | Non-volatile memory with reduced program speed variation | Ashish Baraskar, Yanli Zhang, Raghuveer S. Makala, Yingda Dong | 2019-12-03 |
| 10394649 | First read solution for memory | Idan Alrod, Eran Sharon, Alon Eyal, Evgeny Mekhanik | 2019-08-27 |
| 10372536 | First read solution for memory | Idan Alrod, Eran Sharon, Alon Eyal, Evgeny Mekhanik | 2019-08-06 |
| 10262743 | Command sequence for first read solution for memory | Idan Alrod, Eran Sharon, Alon Eyal, Evgeny Mekhanik | 2019-04-16 |
| 10157676 | Dynamic tuning of first read countermeasures | Yingda Dong, Jiahui Yuan, Charles See Yeung Kwong | 2018-12-18 |
| 10128257 | Select transistors with tight threshold voltage in 3D memory | Jayavel Pachamuthu, Yingda Dong | 2018-11-13 |
| 10121552 | Reducing charge loss in data memory cell adjacent to dummy memory cell | Ashish Baraskar, Yingda Dong, Ching-Huang Lu, Nan Lu, Hong-Yan Chen | 2018-11-06 |
| 10068657 | Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels | Xuehong Yu, Yingda Dong | 2018-09-04 |
| 10020314 | Forming memory cell film in stack opening | Ashish Baraskar, Yanli Zhang, Ching-Huang Lu, Yingda Dong | 2018-07-10 |
| 10008277 | Block health monitoring using threshold voltage of dummy memory cells | Xuehong Yu, Yingda Dong, Nian Niles Yang | 2018-06-26 |
| 9984760 | Suppressing disturb of select gate transistors during erase in memory | Zhengyi Zhang, Yingda Dong | 2018-05-29 |
| 9952944 | First read solution for memory | Idan Alrod, Eran Sharon, Alon Eyal, Evgeny Mekhanik | 2018-04-24 |
| 9941293 | Select transistors with tight threshold voltage in 3D memory | Jayavel Pachamuthu, Yingda Dong | 2018-04-10 |
| 9911500 | Dummy voltage to reduce first read effect in memory | Pao-Ling Koh, Jiahui Yuan, Charles See Yeung Kwong, Yingda Dong | 2018-03-06 |
| 9859298 | Amorphous silicon layer in memory device which reduces neighboring word line interference | Jayavel Pachamuthu, Yingda Dong | 2018-01-02 |
| 9852803 | Dummy word line control scheme for non-volatile memory | Vinh Diep, Ching-Huang Lu, Yingda Dong | 2017-12-26 |
| 9830963 | Word line-dependent and temperature-dependent erase depth | Vinh Diep, Ching-Huang Lu, Yingda Dong | 2017-11-28 |
| 9831118 | Reducing neighboring word line in interference using low-k oxide | Yingda Dong, Jayavel Pachamuthu, Ching-Huang Lu | 2017-11-28 |
| 9812462 | Memory hole size variation in a 3D stacked memory | Ashish Baraskar, Yanli Zhang, Yingda Dong | 2017-11-07 |
| 9800232 | Stitchable global clock for 3D chips | Robert L. Franch, Eren Kursun, Phillip J. Restle | 2017-10-24 |
| 9793283 | High conductivity channel for 3D memory | Jayavel Pachamuthu, Yingda Dong | 2017-10-17 |
| 9786378 | Equalizing erase depth in different blocks of memory cells | Zhengyi Zhang, Caifu Zeng, Xuehong Yu, Yingda Dong | 2017-10-10 |
| 9748266 | Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof | Ashish Baraskar, Yanli Zhang, Ching-Huang Lu, Matthias Baenninger, Yingda Dong | 2017-08-29 |
| 9715937 | Dynamic tuning of first read countermeasures | Yingda Dong, Jiahui Yuan, Charles See Yeung Kwong | 2017-07-25 |
| 9673216 | Method of forming memory cell film | Ashish Baraskar, Yingda Dong, Ching-Huang Lu | 2017-06-06 |