Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308074 | Enhanced gradient seeding scheme during a program operation in a memory sub-system | Ching-Huang Lu, Yingda Dong | 2025-05-20 |
| 12300322 | Selective increase and decrease to pass voltages for programming a memory device | Jeffrey Ming-Hung Tsai, Ching-Huang Lu, Yingda Dong | 2025-05-13 |
| 12237015 | Adaptive sensing time for memory operations | Yu-Chung Lien, Vivek Shivhare, Zhenming Zhou | 2025-02-25 |
| 12217801 | Bias voltage schemes during pre-programming and programming phases | Yingda Dong, Ching-Huang Lu | 2025-02-04 |
| 11967387 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Ching-Huang Lu, Zhengyi Zhang, Yingda Dong | 2024-04-23 |
| 11901010 | Enhanced gradient seeding scheme during a program operation in a memory sub-system | Ching-Huang Lu, Yingda Dong | 2024-02-13 |
| 11508449 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Ching-Huang Lu, Zhengyi Zhang, Yingda Dong | 2022-11-22 |
| 11417834 | Apparatus for spin injection enhancement and method of making the same | Shehrin Sayed, Kerem Y. Camsari, Supriyo Datta | 2022-08-16 |
| 11037640 | Multi-pass programming process for memory device which omits verify test in first program pass | Ashish Baraskar, Ching-Huang Lu, Yingda Dong | 2021-06-15 |
| 11024387 | Memory device with compensation for program speed variations due to block oxide thinning | Ching-Huang Lu, Ashish Baraskar | 2021-06-01 |
| 10923197 | Memory device with compensation for erase speed variations due to blocking oxide layer thinning | Ching-Huang Lu, Ashish Baraskar | 2021-02-16 |
| 10878914 | Memory device with compensation for program speed variations due to block oxide thinning | Ching-Huang Lu, Ashish Baraskar | 2020-12-29 |
| 10854300 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Ching-Huang Lu, Zhengyi Zhang | 2020-12-01 |
| 10811109 | Multi-pass programming process for memory device which omits verify test in first program pass | Ashish Baraskar, Ching-Huang Lu, Yingda Dong | 2020-10-20 |
| 10741253 | Memory device with compensation for erase speed variations due to blocking oxide layer thinning | Ching-Huang Lu, Ashish Baraskar | 2020-08-11 |
| 10706941 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Ching-Huang Lu, Zhengyi Zhang | 2020-07-07 |
| 10665301 | Memory device with compensation for program speed variations due to block oxide thinning | Ching-Huang Lu, Ashish Baraskar | 2020-05-26 |
| 10636501 | Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line | Han-Ping Chen, Ching-Huang Lu, Changyuan Chen | 2020-04-28 |
| 10566059 | Three dimensional NAND memory device with drain select gate electrode shared between multiple strings | Ching-Huang Lu, Henry Chin, Changyuan Chen | 2020-02-18 |
| 10516098 | Apparatus for spin injection enhancement and method of making the same | Shehrin Sayed, Kerem Y. Camsari, Supriyo Datta | 2019-12-24 |
| 10510413 | Multi-pass programming with modified pass voltages to tighten threshold voltage distributions | Ching-Huang Lu | 2019-12-17 |
| 10482981 | Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors | Ching-Huang Lu | 2019-11-19 |
| 10446244 | Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming | Ching-Huang Lu, Zhengyi Zhang, Yingda Dong | 2019-10-15 |
| 10276248 | Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift | Ching-Huang Lu | 2019-04-30 |
| 10068651 | Channel pre-charge to suppress disturb of select gate transistors during erase in memory | Wei Zhao, Ashish Baraskar, Ching-Huang Lu, Yingda Dong | 2018-09-04 |