Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431198 | Charge loss acceleration during programming of memory cells in a memory sub-system | Sheyang Ning, Lawrence Celso Miranda | 2025-09-30 |
| 12254927 | In-line programming adjustment of a memory cell in a memory sub-system | Sheyang Ning, Lawrence Celso Miranda, Tomoko Ogura Iwasaki | 2025-03-18 |
| 12040959 | Traffic monitoring method, apparatus, integrated circuit, network device, and network system | Jing Hu, Feiran Yang, Haifeng Wu, Wei Song | 2024-07-16 |
| 12014778 | In-line programming adjustment of a memory cell in a memory sub-system | Sheyang Ning, Lawrence Celso Miranda, Tomoko Ogura Iwasaki | 2024-06-18 |
| 11967387 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Ching-Huang Lu, Vinh Diep, Yingda Dong | 2024-04-23 |
| 11916881 | Rule detection method and related device | Feiran Yang, Jian Zhang, Jing Hu, Jun Gong | 2024-02-27 |
| 11882047 | Traffic classification method and apparatus | Jing Hu, Shuzhen Tian | 2024-01-23 |
| 11777826 | Traffic monitoring method and apparatus, integrated circuit, and network device | Jing Hu, Feiran Yang, Haifeng Wu, Wei Song | 2023-10-03 |
| 11538535 | Apparatus for rapid data destruction | Dan Xu, Tomoko Ogura Iwasaki | 2022-12-27 |
| 11508449 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Ching-Huang Lu, Vinh Diep, Yingda Dong | 2022-11-22 |
| 11087851 | Apparatus and methods for rapid data destruction | Dan Xu, Tomoko Ogura Iwasaki | 2021-08-10 |
| 10854300 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Ching-Huang Lu, Vinh Diep | 2020-12-01 |
| 10762973 | Suppressing program disturb during program recovery in memory device | Ching-Huang Lu | 2020-09-01 |
| 10748627 | Reducing neighbor word line interference in a two-tier memory device by modifying word line programming order | Hong-Yan Chen, Yingda Dong | 2020-08-18 |
| 10706941 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Ching-Huang Lu, Vinh Diep | 2020-07-07 |
| 10446244 | Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming | Vinh Diep, Ching-Huang Lu, Yingda Dong | 2019-10-15 |
| 10431313 | Grouping memory cells into sub-blocks for program speed uniformity | Yingda Dong, James Kai, Johann Alsmeier | 2019-10-01 |
| 10424387 | Reducing widening of threshold voltage distributions in a memory device due to temperature change | Yingda Dong | 2019-09-24 |
| 10297330 | Separate drain-side dummy word lines within a block to reduce program disturb | Henry Chin, Yingda Dong | 2019-05-21 |
| 10134479 | Non-volatile memory with reduced program speed variation | Yingda Dong | 2018-11-20 |
| 10038005 | Sense circuit having bit line clamp transistors with different threshold voltages for selectively boosting current in NAND strings | Henry Chin, Yingda Dong | 2018-07-31 |
| 9984760 | Suppressing disturb of select gate transistors during erase in memory | Liang Pang, Yingda Dong | 2018-05-29 |
| 9959932 | Grouping memory cells into sub-blocks for program speed uniformity | Yingda Dong, James Kai, Johann Alsmeier | 2018-05-01 |
| 9922705 | Reducing select gate injection disturb at the beginning of an erase operation | Vinh Diep, Xuehong Yu, Yingda Dong | 2018-03-20 |
| 9887002 | Dummy word line bias ramp rate during programming | Yingda Dong | 2018-02-06 |