Issued Patents All Time
Showing 26–50 of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9991167 | Method and IC structure for increasing pitch between gates | Arvind Kumar, Murshed Chowdhury, Brian J. Greene | 2018-06-05 |
| 9922831 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-03-20 |
| 9899525 | Increased contact area for finFETs | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2018-02-20 |
| 9859122 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-01-02 |
| 9837319 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-12-05 |
| 9825094 | FinFET PCM access transistor having gate-wrapped source and drain regions | Chung H. Lam, Darsen D. Lu, Philip J. Oldiges | 2017-11-21 |
| 9825093 | FinFET PCM access transistor having gate-wrapped source and drain regions | Chung H. Lam, Darsen D. Lu, Philip J. Oldiges | 2017-11-21 |
| 9768071 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-09-19 |
| 9721843 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-08-01 |
| 9716036 | Electronic device including moat power metallization in trench | Josephine B. Chang, Leland Chang, Michael A. Guillorn, Adam M. Pyzyna | 2017-07-25 |
| 9711648 | Structure and method for CMP-free III-V isolation | Effendi Leobandung, Amlan Majumdar, Yanning Sun | 2017-07-18 |
| 9685379 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-06-20 |
| 9680020 | Increased contact area for FinFETs | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2017-06-13 |
| 9653615 | Hybrid ETSOI structure to minimize noise coupling from TSV | Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman | 2017-05-16 |
| 9646883 | Chemoepitaxy etch trim using a self aligned hard mask for metal line to via | Markus Brink, Michael A. Guillorn, HsinYu Tsai | 2017-05-09 |
| 9601576 | Nanowire FET with tensile channel stressor | Isaac Lauer, Jeffrey W. Sleight | 2017-03-21 |
| 9583624 | Asymmetric finFET memory access transistor | Chung H. Lam, Darsen D. Lu, Philip J. Oldiges | 2017-02-28 |
| 9577061 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-02-21 |
| 9570354 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-02-14 |
| 9559010 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-01-31 |
| 9553173 | Asymmetric finFET memory access transistor | Chung H. Lam, Darsen D. Lu, Philip J. Oldiges | 2017-01-24 |
| 9543213 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-01-10 |
| 9530876 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2016-12-27 |
| 9530860 | III-V MOSFETs with halo-doped bottom barrier layer | Pranita Kerber, Amlan Majumdar, Jeffrey W. Sleight | 2016-12-27 |
| 9412667 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2016-08-09 |