Issued Patents All Time
Showing 76–100 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7645645 | Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof | William Paul Hovis, Louis L. Hsu, William R. Tonti, Chih-Chao Yang | 2010-01-12 |
| 7642588 | Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same | Kangguo Cheng | 2010-01-05 |
| 7638381 | Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby | Kangguo Cheng | 2009-12-29 |
| 7622946 | Design structure for an automatic driver/transmission line/receiver impedance matching circuitry | Wagdi W. Abadeer, Louis L. Hsu | 2009-11-24 |
| 7618872 | Semiconductor device structures for bipolar junction transistors and methods of fabricating such structures | Kangguo Cheng, Louis L. Hsu | 2009-11-17 |
| 7615828 | CMOS devices adapted to prevent latchup and methods of manufacturing the same | William R. Tonti | 2009-11-10 |
| 7611931 | Semiconductor structures with body contacts and fabrication methods thereof | Kangguo Cheng, Ramachandra Divakaruni | 2009-11-03 |
| 7608506 | Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures | Kangguo Cheng, Louis L. Hsu | 2009-10-27 |
| 7592247 | Sub-lithographic local interconnects, and methods for forming same | Haining Yang, Wai-Kin Li | 2009-09-22 |
| 7572682 | Semiconductor structure for fuse and anti-fuse applications | Chih-Chao Yang, Daniel C. Edelstein, Louis L. Hsu | 2009-08-11 |
| 7569434 | PFETs and methods of manufacturing the same | Kangguo Cheng, Louis L. Hsu, Haining Yang | 2009-08-04 |
| 7566629 | Patterned silicon-on-insulator layers and methods for forming the same | Roger A. Booth, Jr., Louis L. Hsu, William R. Tonti | 2009-07-28 |
| 7560784 | Fin PIN diode | Kangguo Cheng, Louis L. Hsu | 2009-07-14 |
| 7560310 | Semiconductor constructions and semiconductor device fabrication methods | Louis L. Hsu, Rajiv V. Joshi | 2009-07-14 |
| 7550773 | FinFET with top body contact | Roger A. Booth, Jr., Kangguo Cheng | 2009-06-23 |
| 7545253 | Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer | Louis L. Hsu, William R. Tonti, Chih-Chao Yang | 2009-06-09 |
| 7531423 | Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same | Kangguo Cheng, Louis L. Hsu, Haining Yang | 2009-05-12 |
| 7531388 | Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof | Roger A. Booth, Jr., William R. Tonti | 2009-05-12 |
| 7525170 | Pillar P-i-n semiconductor diodes | Louis L. Hsu, Kangguo Cheng | 2009-04-28 |
| 7525121 | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same | Louis L. Hsu | 2009-04-28 |
| 7521776 | Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers | Ethan H. Cannon, Toshiharu Furukawa, Charles W. Koburger, III, William R. Tonti | 2009-04-21 |
| 7518191 | Silicon on insulator devices having body-tied-to-source and methods of making | Thomas W. Dyer, Keith Kwong Hon Wong, Chih-Chao Yang, Haining Yang | 2009-04-14 |
| 7517764 | Bulk FinFET device | Roger A. Booth, Jr., William Paul Hovis | 2009-04-14 |
| 7514323 | Vertical SOI trench SONOS cell | David M. Dobuzinsky, Herbert L. Ho, Yoichi Otani | 2009-04-07 |
| 7494916 | Design structures incorporating interconnect structures with liner repair layers | Louis L. Hsu, William R. Tonti, Chih-Chao Yang | 2009-02-24 |