Issued Patents All Time
Showing 126–150 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7358823 | Programmable capacitors and methods of using the same | Wagdi W. Abadeer, Anthony R. Bonaccio, William R. Tonti, Sebastian T. Ventrone | 2008-04-15 |
| 7358573 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same | Delbert R. Cecchi, Toshiharu Furukawa | 2008-04-15 |
| 7358164 | Crystal imprinting methods for fabricating substrates with thin active silicon layers | Louis L. Hsu, William R. Tonti | 2008-04-15 |
| 7358120 | Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2008-04-15 |
| 7352034 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures | Roger A. Booth, Jr., William R. Tonti | 2008-04-01 |
| 7348280 | Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions | Louis L. Hsu, William R. Tonti, Chih-Chao Yang | 2008-03-25 |
| 7335599 | Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate | Howard H. Chen, Louis L. Hsu | 2008-02-26 |
| 7335575 | Semiconductor constructions and semiconductor device fabrication methods | Louis L. Hsu, Rajiv V. Joshi | 2008-02-26 |
| 7288804 | Electrically programmable π-shaped fuse structures and methods of fabrication thereof | Roger A. Booth, Jr., Kangguo Cheng, William R. Tonti | 2007-10-30 |
| 7283410 | Real-time adaptive SRAM array for high SEU immunity | Louis L. Hsu, Robert C. Wong, Chih-Chao Yang | 2007-10-16 |
| 7276768 | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures | Toshiharu Furukawa, Robert J. Gauthier, Jr., David V. Horak, Charles W. Koburger, III, William R. Tonti | 2007-10-02 |
| 7276775 | Intrinsic dual gate oxide MOSFET using a damascene gate process | Claude L. Bertin, Anthony J. Dally, John A. Fifield, John Jesse Higgins, William R. Tonti +1 more | 2007-10-02 |
| 7268400 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same | Delbert R. Cecchi, Toshiharu Furukawa | 2007-09-11 |
| 7268028 | Well isolation trenches (WIT) for CMOS devices | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, William R. Tonti | 2007-09-11 |
| 7265696 | Methods and apparatus for testing an integrated circuit | Louis L. Hsu, Joseph O. Marsh, Steven J. Zier | 2007-09-04 |
| 7262451 | High performance embedded DRAM technology with strained silicon | Jeffrey P. Gambino, Geng Wang | 2007-08-28 |
| 7232745 | Body capacitor for SOI memory description | Louis C. Hsu, Rajiv V. Joshi | 2007-06-19 |
| 7226816 | Method of forming connection and anti-fuse in layered substrate such as SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2007-06-05 |
| 7227233 | Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2007-06-05 |
| 7227230 | Low-K gate spacers by fluorine implantation | Jeffrey P. Gambino, William R. Tonti | 2007-06-05 |
| 7205816 | Variable-gain-amplifier based limiter to remove amplitude modulation from a VCO output | Herschel A. Ainspan, Gautam Gangasani, Louis C. Hsu | 2007-04-17 |
| 7190042 | Self-aligned STI for narrow trenches | Ramachandra Divakaruni, Carl Radens | 2007-03-13 |
| 7138685 | Vertical MOSFET SRAM cell | Louis L. Hsu, Oleg Gluschenkov, Carl Radens | 2006-11-21 |
| 7113006 | Capacitor reliability for multiple-voltage power supply systems | Louis L. Hsu, Rajiv V. Joshi | 2006-09-26 |
| 7087948 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Carl Radens, Richard Strub, William R. Tonti | 2006-08-08 |