Issued Patents All Time
Showing 151–175 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7026202 | Inverse-T gate structure using damascene processing | Carl Radens, William R. Tonti | 2006-04-11 |
| 7023041 | Trench capacitor vertical structure | Giuseppe La Rosa, Thomas W. Dyer, Oleg Gluschenkov, Carl Radens, Alvin W. Strong | 2006-04-04 |
| 6979851 | Structure and method of vertical transistor DRAM cell having a low leakage buried strap | Dureseti Chidambarrao, Carl Radens | 2005-12-27 |
| 6974743 | Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates | Ramac Divakaruni, Stephan Kudelka | 2005-12-13 |
| 6972220 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2005-12-06 |
| 6967137 | Forming collar structures in deep trench capacitors with thermally stable filler material | Michael P. Belyansky, Rama Divakaruni, Dae-Gyu Park | 2005-11-22 |
| 6911687 | Buried bit line-field isolation defined active semiconductor areas | Gerhard Kunkel | 2005-06-28 |
| 6909137 | Method of creating deep trench capacitor using a P+ metal electrode | Ramachandra Divakaruni, Dae-Gyu Park | 2005-06-21 |
| 6897107 | Method for forming TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Thomas W. Dyer, Rajeev Malik, Venkatachajam C. Jaiprakash | 2005-05-24 |
| 6872620 | Trench capacitors with reduced polysilicon stress | Dureseti Chidambarrao, Rajarao Jammy | 2005-03-29 |
| 6869846 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Carl Radens, Richard Strub, William R. Tonti | 2005-03-22 |
| 6833305 | Vertical DRAM punchthrough stop self-aligned to storage trench | Dureseti Chidambarrao, Ramachandra Divakaruni | 2004-12-21 |
| 6831006 | Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner | Ramachandra Divakaruni, Haining Yang | 2004-12-14 |
| 6818487 | Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof | Louis L. Hsu, William R. Tonti, Li-Kong Wang | 2004-11-16 |
| 6818528 | Method for multi-depth trench isolation | Ramachandra Divakaruni | 2004-11-16 |
| 6815749 | Backside buried strap for SOI DRAM trench capacitor | Herbert L. Ho | 2004-11-09 |
| 6809372 | Flash memory structure using sidewall floating gate | Jeffrey P. Gambino, Louis L. Hsu, Donald C. Wheeler | 2004-10-26 |
| 6808981 | Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI | Ramachandra Divakaruni, Carl Radens, Gary B. Bronner | 2004-10-26 |
| 6809368 | TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Thomas W. Dyer, Rajeev Malik, Venkatachalam C. Jaiprakash | 2004-10-26 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor | Ramachandra Divakaruni, Russell J. Houghton, Wilbur D. Pricer, William R. Tonti | 2004-09-14 |
| 6777733 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Ramachandra Divakaruni, Carl Radens | 2004-08-17 |
| 6777737 | Vertical DRAM punchthrough stop self-aligned to storage trench | Dureseti Chidambarrao, Ramachandra Divakaruni | 2004-08-17 |
| 6767789 | Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby | Gary B. Bronner, David V. Horak, Toshiharu Furukawa | 2004-07-27 |
| 6762447 | Field-shield-trench isolation for gigabit DRAMs | Rama Divakaruni, Giuseppe Larosa, Ulrike Gruening, Carl Radens | 2004-07-13 |
| 6759291 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2004-07-06 |