Issued Patents All Time
Showing 201–225 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6635525 | Method of making backside buried strap for SOI DRAM trench capacitor | Herbert L. Ho | 2003-10-21 |
| 6632741 | Self-trimming method on looped patterns | Lawrence A. Clevenger, Louis L. Hsu, Carl Radens | 2003-10-14 |
| 6630379 | Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch | Ramachandra Divakaruni, Carl Radens, Ulrike Gruening | 2003-10-07 |
| 6617702 | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate | Louis L. Hsu, Rajiv V. Joshi, Carl Radens, Tsorng-Dih Yuan | 2003-09-09 |
| 6614074 | Grooved planar DRAM transfer device using buried pocket | Gary B. Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak | 2003-09-02 |
| 6605838 | Process flow for thick isolation collar with reduced length | Rama Divakaruni, Gerd Fehlauer, Stephan Kudelka, Uwe Schroeder, Helmut Tews | 2003-08-12 |
| 6596592 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2003-07-22 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate | James W. Adkisson, Ramachandra Divakaruni, Jeffrey P. Gambino | 2003-07-08 |
| 6580136 | Method for delineation of eDRAM support device notched gate | Carl Radens | 2003-06-17 |
| 6576945 | Structure and method for a compact trench-capacitor DRAM cell with body contact | Carl Radens | 2003-06-10 |
| 6573585 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Dureseti Chidambarrao, Louis L. Hsu, Carl Radens | 2003-06-03 |
| 6573137 | Single sided buried strap | Ramachandra Divakaruni, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening, Stephan Kudelka +5 more | 2003-06-03 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping | Dureseti Chidambarrao, Ramachandra Divakaruni, Kevin McStay | 2003-06-03 |
| 6570207 | Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex | Louis L. Hsu, Carl Radens, William R. Tonti | 2003-05-27 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI | Ramachandra Divakaruni, Carl Radens, Gary B. Bronner | 2003-05-27 |
| 6566191 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Carl Radens, Richard Strub, William R. Tonti | 2003-05-20 |
| 6566228 | Trench isolation processes using polysilicon-assisted fill | Jochen Beintner, Rama Divakaruni, Andreas Knorr | 2003-05-20 |
| 6566177 | Silicon-on-insulator vertical array device trench capacitor DRAM | Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Dan Moy +3 more | 2003-05-20 |
| 6563736 | Flash memory structure having double celled elements and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi, Carl Radens, William R. Tonti | 2003-05-13 |
| 6555862 | Self-aligned buried strap for vertical transistors | Ulrike Gruening, Alexander Michaelis | 2003-04-29 |
| 6552378 | Ultra compact DRAM cell and method of making | Heinz Hoenigschmid, Louis L. Hsu | 2003-04-22 |
| 6548358 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Dureseti Chidambarrao, Louis L. Hsu, Carl Radens | 2003-04-15 |
| 6544837 | SOI stacked DRAM logic | Ramachandra Divakauni, Mark C. Hakey, William H. Ma, William R. Tonti | 2003-04-08 |
| 6541815 | High-density dual-cell flash memory structure | Louis L. Hsu, Chung H. Lam, Carl Radens | 2003-04-01 |
| 6538295 | Salicide device with borderless contact | Gary B. Bronner, Jeffrey P. Gambino, Louis L. Hsu, Carl Radens, William R. Tonti | 2003-03-25 |