Issued Patents All Time
Showing 251–275 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6441423 | Trench capacitor with an intrinsically balanced field across the dielectric | Rama Divakaruni | 2002-08-27 |
| 6440788 | Implant sequence for multi-function semiconductor structure and method | Edward J. Nowak, William R. Tonti | 2002-08-27 |
| 6440793 | Vertical MOSFET | Ramachandra Divakaruni, Heon Lee, Carl Radens, Jai-Hoon Sim | 2002-08-27 |
| 6440801 | Structure for folded architecture pillar memory cell | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Howard L. Kalter +2 more | 2002-08-27 |
| 6437401 | Structure and method for improved isolation in trench storage cells | Stephan Kudelka, Andreas Knorr, Stephen Rahn, Helmut Tews, Michael Wise | 2002-08-20 |
| 6437388 | Compact trench capacitor memory cell with body contact | Carl Radens, Ulrike Gruening | 2002-08-20 |
| 6436749 | Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion | William R. Tonti, Claude L. Bertin, Jeffrey P. Gambino, Russell J. Houghton, Wilbur D. Pricer | 2002-08-20 |
| 6432787 | Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact | Ramachandra Divakaruni | 2002-08-13 |
| 6429477 | Shared body and diffusion contact structure and method for fabricating same | Rama Divakaruni, William R. Tonti | 2002-08-06 |
| 6429068 | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Larry Nesbit, Carl Radens | 2002-08-06 |
| 6426251 | Process for manufacturing a crystal axis-aligned vertical side wall device | Gary B. Bronner, Ulrike Gruening, Carl Radens | 2002-07-30 |
| 6426530 | High performance direct coupled FET memory cell | Claude L. Bertin, John Cronin, Erik L. Hedberg | 2002-07-30 |
| 6426526 | Single sided buried strap | Ramachandra Divakaruni, Gary B. Bronner, Carl Radens | 2002-07-30 |
| 6426252 | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap | Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Dan Moy +3 more | 2002-07-30 |
| 6426247 | Low bitline capacitance structure and method of making same | Ramachandra Divakaruni, Jeffrey P. Gambino, Rajesh Rengarajan | 2002-07-30 |
| 6424011 | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate | Fariborz Assaderaghi, Louis L. Hsu | 2002-07-23 |
| 6420749 | Trench field shield in trench isolation | Ramachandra Divakaruni, Jeffrey P. Gambino, Edward W. Kiewra, Carl Radens, William R. Tonti | 2002-07-16 |
| 6420750 | Structure and method for buried-strap with reduced outdiffusion | Ramachandra Divakaruni | 2002-07-16 |
| 6414347 | Vertical MOSFET | Ramachandra Divakaruni, Heon Lee, Carl Radens, Jai-Hoon Sim | 2002-07-02 |
| 6410369 | Soi-body selective link method and apparatus | Roy C. Flaker, Louis L. Hsu, Fariborz Assaderaghi | 2002-06-25 |
| 6404000 | Pedestal collar structure for higher charge retention time in trench-type DRAM cells | Rama Divakaruni, Rajarao Jammy, Byeong Y. Kim, Akira Sudo, Dirk Tobben | 2002-06-11 |
| 6399447 | Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor | Lawrence A. Clevenger, Louis L. Hsu, Carl Radens | 2002-06-04 |
| 6396121 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2002-05-28 |
| 6396120 | Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application | Claude L. Bertin, Toshiharu Furukawa, Erik L. Hedberg, William R. Tonti, Richard Q. Williams | 2002-05-28 |
| 6380027 | Dual tox trench dram structures and process using V-groove | Toshiharu Furukawa, Jeffrey P. Gambino, Edward W. Kiewra, Carl Radens, William R. Tonti +1 more | 2002-04-30 |