Issued Patents All Time
Showing 301–325 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6288422 | Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance | Rama Divakaruni, Carl Radens | 2001-09-11 |
| 6284593 | Method for shallow trench isolated, contacted well, vertical MOSFET DRAM | Ramachandra Divakaruni, Carl Radens | 2001-09-04 |
| 6281539 | Structure and process for 6F2 DT cell having vertical MOSFET and large storage capacitance | Rama Divakaruni | 2001-08-28 |
| 6281064 | Method for providing dual work function doping and protective insulating cap | Gary B. Bronner, Ramachandra Divakaruni | 2001-08-28 |
| 6278171 | Sublithographic fuses using a phase shift mask | Kenneth C. Arndt, Louis L. Hsu, K. Paul Muller | 2001-08-21 |
| 6274441 | Method of forming bitline diffusion halo under gate conductor ledge | Ramachandra Divakaruni, William R. Tonti | 2001-08-14 |
| 6274467 | Dual work function gate conductors with self-aligned insulating cap | Jeffrey P. Gambino, Louis L. Hsu, Carl Radens, William R. Tonti | 2001-08-14 |
| 6271093 | Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs | Johan Alsmeier | 2001-08-07 |
| 6271080 | Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity | Toshiharu Furukawa, William R. Tonti | 2001-08-07 |
| 6265278 | Deep trench cell capacitor with inverting counter electrode | Johann Alsmeier, James A. O'Neill, Christopher C. Parks, Paul C. Parries | 2001-07-24 |
| 6265279 | Method for fabricating a trench capacitor | Carl Radens, Joachim Hoepfner | 2001-07-24 |
| 6261894 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Ramachandra Divakaruni, Carl Radens | 2001-07-17 |
| 6261924 | Maskless process for self-aligned contacts | Heon Lee, Young Jin Park | 2001-07-17 |
| 6259126 | Low cost mixed memory integration with FERAM | Louis L. Hsu, Fariborz Assaderaghi | 2001-07-10 |
| 6259129 | Strap with intrinsically conductive barrier | Jeffrey P. Gambino, Rajarao Jammy, Carl Radens | 2001-07-10 |
| 6258689 | Low resistance fill for deep trench capacitor | Gary B. Bronner, Jeffrey P. Gambino, Rick L. Mohler, Carl Radens, William R. Tonti | 2001-07-10 |
| 6258659 | Embedded vertical DRAM cells and dual workfunction logic gates | Ulrike Gruening, Ramachandra Divakaruni, Thomas Rupp | 2001-07-10 |
| 6255157 | Method for forming a ferroelectric capacitor under the bit line | Louis L. Hsu, David E. Kotecki | 2001-07-03 |
| 6255899 | Method and apparatus for increasing interchip communications rates | Claude L. Bertin, Anthony R. Bonaccio, Erik L. Hedberg, Howard L. Kalter, Thomas M. Maffitt +2 more | 2001-07-03 |
| 6255699 | Pillar CMOS structure | John A. Bracchitta, Stephen A. Parke, Matthew R. Wordeman | 2001-07-03 |
| 6255694 | Multi-function semiconductor structure and method | Edward J. Nowak, William R. Tonti | 2001-07-03 |
| 6255683 | Dynamic random access memory | Carl Radens, Ulrike Gruening, John K. DeBrosse | 2001-07-03 |
| 6255158 | Process of manufacturing a vertical dynamic random access memory device | Toshiharu Furukawa, Ulrike Gruening, David V. Horak, Carl Radens, Thomas Rupp | 2001-07-03 |
| 6252271 | Flash memory structure using sidewall floating gate and method for forming the same | Jeffrey P. Gambino, Louis L. Hsu, Donald C. Wheeler | 2001-06-26 |
| 6245613 | Field effect transistor having a floating gate | Louis L. Hsu, Chih-Chun Hu | 2001-06-12 |