Issued Patents All Time
Showing 276–300 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6376324 | Collar process for reduced deep trench edge bias | Ramachandra Divakaruni, Carl Radens, Ulrike Gruening, Akira Sudo | 2002-04-23 |
| 6373086 | Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same | Rama Divakaruni, Byeong Y. Kim | 2002-04-16 |
| 6369671 | Voltage controlled transmission line with real-time adaptive control | Claude L. Bertin, Anthony R. Bonaccio, Howard L. Kalter, Thomas M. Maffitt, Edward J. Nowak +1 more | 2002-04-09 |
| 6369419 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2002-04-09 |
| 6362056 | Method of making alternative to dual gate oxide for MOSFETs | William R. Tonti | 2002-03-26 |
| 6355531 | Method for fabricating semiconductor devices with different properties using maskless process | Louis L. Hsu, Carl Radens, William R. Tonti, Li-Kong Wang | 2002-03-12 |
| 6352882 | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation | Fariborz Assaderaghi, Louis L. Hsu | 2002-03-05 |
| 6352892 | Method of making DRAM trench capacitor | Rajarao Jammy, Carl Radens | 2002-03-05 |
| 6350653 | Embedded DRAM on silicon-on-insulator substrate | James W. Adkisson, Ramachandra Divakaruni, Jeffrey P. Gambino | 2002-02-26 |
| 6348394 | Method and device for array threshold voltage control by trapped charge in trench isolation | Rama Divakaruni, Herbert L. Ho, Giuseppe La Rosa, Yujun Li, Jochen Beintner +1 more | 2002-02-19 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening, Carl Radens | 2002-02-19 |
| 6344381 | Method for forming pillar CMOS | John A. Bracchitta, Stephen A. Parke, Matthew R. Wordeman | 2002-02-05 |
| 6344383 | Structure and method for dual gate oxidation for CMOS technology | Wayne S. Berry, Jeffrey P. Gambino, William R. Tonti | 2002-02-05 |
| 6339241 | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch | Ramachandra Divakaruni, Carl Radens, Ulrike Gruening | 2002-01-15 |
| 6335239 | Manufacturing a DRAM cell having an annular signal transfer region | Farid Agahi, Louis L. Hsu | 2002-01-01 |
| 6333220 | Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact | Ramachandra Divakaruni | 2001-12-25 |
| 6333533 | Trench storage DRAM cell with vertical three-sided transfer device | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Thomas S. Kanarsky | 2001-12-25 |
| 6323086 | Flash memory structure using sidewall floating gate having one side thereof surrounded by control gate | Louis L. Hsu | 2001-11-27 |
| 6323082 | Process for making a DRAM cell with three-sided gate transfer | Toshiharu Furukawa, David V. Horak, Steven J. Holmes, Mark C. Hakey | 2001-11-27 |
| 6323532 | Deep divot mask for enhanced buried-channel PFET performance and reliability | Hans-Oliver Joachim, Rajesh Rengarajah | 2001-11-27 |
| 6320215 | Crystal-axis-aligned vertical side wall device | Gary B. Bronner, Ulrike Gruening, Carl Radens | 2001-11-20 |
| 6319794 | Structure and method for producing low leakage isolation devices | Hiroyuki Akatsu, Tze-Chiang Chen, Laertis Economikos, Herbert L. Ho, Richard L. Kleinhenz +1 more | 2001-11-20 |
| 6309924 | Method of forming self-limiting polysilicon LOCOS for DRAM cell | Ramachandra Divakaruni, Irene McStay, Larry Nesbit, Carl Radens, Helmut Tews | 2001-10-30 |
| 6297531 | High performance, low power vertical integrated CMOS devices | Michael D. Armacost, Claude L. Bertin, Erik L. Hedberg | 2001-10-02 |
| 6297086 | Application of excimer laser anneal to DRAM processing | Suryanarayan G. Hegde, Kam-Leung Lee, Carl Radens | 2001-10-02 |