Issued Patents All Time
Showing 326–350 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6242310 | Method of forming buried-strap with reduced outdiffusion including removing a sacrificial insulator leaving a gap and supporting spacer | Ramachandra Divakaruni | 2001-06-05 |
| 6239649 | Switched body SOI (silicon on insulator) circuits and fabrication method therefor | Claude L. Bertin, John J. Ellis-Monaghan, Erik L. Hedberg, Terence B. Hook, Edward J. Nowak +3 more | 2001-05-29 |
| 6236077 | Trench electrode with intermediate conductive barrier layer | Jeffrey P. Gambino, Rajarao Jammy, Carl Radens | 2001-05-22 |
| 6232173 | Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure | Louis L. Hsu, Fariborz Assaderaghi | 2001-05-15 |
| 6228745 | Selective reduction of sidewall slope on isolation edge | Donald C. Wheeler, Louis L. Hsu, Rebecca D. Mih | 2001-05-08 |
| 6225158 | Trench storage dynamic random access memory cell with vertical transfer device | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William H. Ma | 2001-05-01 |
| 6222244 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Dureseti Chidambarrao, Louis L. Hsu, Carl Radens | 2001-04-24 |
| 6222218 | DRAM trench | Rajarao Jammy, Carl Radens | 2001-04-24 |
| 6207540 | Method for manufacturing high performance MOSFET device with raised source and drain | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, William H. Ma | 2001-03-27 |
| 6204532 | Pillar transistor incorporating a body contact | Jeffrey P. Gambino, Stephen A. Parke, Matthew R. Wordeman | 2001-03-20 |
| 6204140 | Dynamic random access memory | Ulrike Gruening, Jochen Beintner, Scott D. Halle, Carl Radens, Juergen Wittmann +1 more | 2001-03-20 |
| 6194755 | Low-resistance salicide fill for trench capacitors | Jeffrey P. Gambino, Ulrike Gruening, Carl Radens | 2001-02-27 |
| 6194736 | Quantum conductive recrystallization barrier layers | Susan E. Chaloux, Tze-Chiang Chen, Johnathan E. Faltermeier, Ulrike Gruening, Rajarao Jammy +4 more | 2001-02-27 |
| 6190959 | Semiconductor memory array having sublithographic spacing between adjacent trenches and method for making the same | Gary B. Bronner, Donald J. Samuels | 2001-02-20 |
| 6190986 | Method of producing sulithographic fuses using a phase shift mask | Kenneth C. Arndt, Louis L. Hsu, K. Paul Muller | 2001-02-20 |
| 6184107 | Capacitor trench-top dielectric for self-aligned device isolation | Rama Divakaruni, Ulrike Gruening, Byeong Y. Kim, Larry Nesbit, Carl Radens | 2001-02-06 |
| 6184549 | Trench storage dynamic random access memory cell with vertical transfer device | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William H. Ma | 2001-02-06 |
| 6177809 | Redundant input/output driver circuit | William R. Tonti, Anthony R. Bonaccio, Claude L. Bertin, Howard L. Kalter, John A. Fifield | 2001-01-23 |
| 6177299 | Transistor having substantially isolated body and method of making the same | Louis L. Hsu | 2001-01-23 |
| 6177818 | Complementary depletion switch body stack off-chip driver | Claude L. Bertin, Anthony R. Bonaccio, Howard L. Kalter, Thomas M. Maffitt, William R. Tonti | 2001-01-23 |
| 6174762 | Salicide device with borderless contact | Gary B. Bronner, Jeffrey P. Gambino, Louis L. Hsu, Carl Radens, William R. Tonti | 2001-01-16 |
| 6163045 | Reduced parasitic leakage in semiconductor devices | Louis L. Hsu, Johann Alsmeier, William R. Tonti | 2000-12-19 |
| 6153902 | Vertical DRAM cell with wordline self-aligned to storage trench | Toshiharu Furukawa, Ulrike Gruening, David V. Horak, Carl Radens, Thomas Rupp | 2000-11-28 |
| 6153474 | Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate | Herbert L. Ho, Radhika Srinivasan, Scott D. Halle, Erwin Hammerl, David M. Dobuzinsky +1 more | 2000-11-28 |
| 6150212 | Shallow trench isolation method utilizing combination of spacer and fill | Ramachandra Divakaruni, Jeffrey P. Gambino, Carl Radens, William R. Tonti | 2000-11-21 |