Issued Patents All Time
Showing 351–375 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6144081 | Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures | Louis L. Hsu, Chang-Ming Hsieh, Lyndon R. Logan, Seiki Ogura | 2000-11-07 |
| 6144054 | DRAM cell having an annular signal transfer region | Farid Agahi, Louis L. Hsu | 2000-11-07 |
| 6141242 | Low cost mixed memory integration with substantially coplanar gate surfaces | Louis L. Hsu, Fariborz Assaderaghi | 2000-10-31 |
| 6137129 | High performance direct coupled FET memory cell | Claude L. Bertin, John Cronin, Erik L. Hedberg | 2000-10-24 |
| 6136655 | Method of making low voltage active body semiconductor device | Fariborz Assaderaghi, Claude L. Bertin, Jeffrey P. Gambino, Louis L. Hsu | 2000-10-24 |
| 6136664 | Filling of high aspect ratio trench isolation | Laertis Economikos, David E. Kotecki | 2000-10-24 |
| 6133608 | SOI-body selective link method and apparatus | Roy C. Flaker, Louis L. Hsu, Fariborz Assaderaghi | 2000-10-17 |
| 6127215 | Deep pivot mask for enhanced buried-channel PFET performance and reliability | Hans-Oliver Joachim, Rajesh Rengarajan | 2000-10-03 |
| 6121661 | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation | Fariborz Assaderaghi, Louis L. Hsu | 2000-09-19 |
| 6121651 | Dram cell with three-sided-gate transfer device | Toshiharu Furukawa, David V. Horak, Steven J. Holmes, Mark C. Hakey | 2000-09-19 |
| 6114725 | Structure for folded architecture pillar memory cell | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Howard L. Kalter +2 more | 2000-09-05 |
| 6110824 | Wire shape conferring reduced crosstalk and formation methods | Thomas J. Licata | 2000-08-29 |
| 6107133 | Method for making a five square vertical DRAM cell | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William H. Ma | 2000-08-22 |
| 6107125 | SOI/bulk hybrid substrate and method of forming the same | Mark A. Jaso, William R. Tonti, Matthew R. Wordeman | 2000-08-22 |
| 6100123 | Pillar CMOS structure | John A. Bracchitta, Stephen A. Parke, Matthew R. Wordeman | 2000-08-08 |
| 6097070 | MOSFET structure and process for low gate induced drain leakage (GILD) | Carl Radens | 2000-08-01 |
| 6097056 | Field effect transistor having a floating gate | Louis L. Hsu, Chih-Chun Hu | 2000-08-01 |
| 6090671 | Reduction of gate-induced drain leakage in semiconductor devices | Karanam Balasubramanyam, Martin Gall, Jeffrey P. Gambino | 2000-07-18 |
| 6084276 | Threshold voltage tailoring of corner of MOSFET device | Jeffrey P. Gambino, Gary B. Bronner, Larry Nesbit | 2000-07-04 |
| 6069390 | Semiconductor integrated circuits with mesas | Louis L. Hsu | 2000-05-30 |
| 6063658 | Methods of making a trench storage DRAM cell including a step transfer device | David V. Horak, Toshiharu Furukawa, Steven J. Holmes, Mark C. Hakey, William H. Ma | 2000-05-16 |
| 6060746 | Power transistor having vertical FETs and method for making same | Claude L. Bertin, Jeffrey P. Gambino | 2000-05-09 |
| 6049495 | Auto-programmable current limiter to control current leakage due to bitline to wordline short | Louis L. Hsu, Giuseppe La Rosa | 2000-04-11 |
| 6037648 | Semiconductor structure including a conductive fuse and process for fabrication thereof | Kenneth C. Arndt, Jeffrey P. Gambino, Chandrasekhar Narayan, Rainer Florian Schnabel, Ronald J. Schutz +1 more | 2000-03-14 |
| 6037620 | DRAM cell with transfer device extending along perimeter of trench storage capacitor | Heinz Hoenigschmid, Louis L. Hsu | 2000-03-14 |