Issued Patents All Time
Showing 226–250 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6534824 | Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell | Dureseti Chidambarrao | 2003-03-18 |
| 6531410 | Intrinsic dual gate oxide MOSFET using a damascene gate process | Claude L. Bertin, Anthony J. Dally, John A. Fifield, John Jesse Higgins, William R. Tonti +1 more | 2003-03-11 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain | Qiuyi Ye, William R. Tonti, Yujun Li | 2003-03-04 |
| 6524941 | Sub-minimum wiring structure | Louis L. Hsu | 2003-02-25 |
| 6518670 | Electrically porous on-chip decoupling/shielding layer | Ronald G. Filippi, Jeffrey P. Gambino, Richard A. Wachnik | 2003-02-11 |
| 6518641 | Deep slit isolation with controlled void | Ramachandra Divakaruni, Johnathan E. Faltermeier, William R. Tonti | 2003-02-11 |
| 6518119 | Strap with intrinsically conductive barrier | Jeffrey P. Gambino, Rajarao Jammy, Carl Radens | 2003-02-11 |
| 6518118 | Structure and process for buried bitline and single sided buried conductor formation | Satish D. Athavale, Ramachandra Divakaruni | 2003-02-11 |
| 6518112 | High performance, low power vertical integrated CMOS devices | Michael D. Armacost, Claude L. Bertin, Erik L. Hedberg | 2003-02-11 |
| 6512275 | Semiconductor integrated circuits | Louis L. Hsu | 2003-01-28 |
| 6509226 | Process for protecting array top oxide | Venkatachalam C. Jaiprakash, Ramachandra Divakaruni, Rajeev Malik, Mihel Seitz | 2003-01-21 |
| 6504210 | Fully encapsulated damascene gates for Gigabit DRAMs | Ramachandra Divakaruni, Jeffrey P. Gambino, Viraj Y. Sardesai, Mary E. Weybright | 2003-01-07 |
| 6501117 | Static self-refreshing DRAM structure and operating mode | Carl Radens, Gary B. Bronner, Ramachandra Divakaruni | 2002-12-31 |
| 6501131 | Transistors having independently adjustable parameters | Rama Divakaruni, Jeffrey P. Gambino, Rajesh Rengarajan | 2002-12-31 |
| 6498518 | Low input impedance line/bus receiver | Russell J. Houghton, Azzouz Nezar, Wilbur D. Pricer, William R. Tonti | 2002-12-24 |
| 6492211 | Method for novel SOI DRAM BICMOS NPN | Ramachandra Divakaruni, Russell J. Houghton, W. David Pricer, William R. Tonti | 2002-12-10 |
| 6479368 | Method of manufacturing a semiconductor device having a shallow trench isolating region | Mutsuo Morikado, Herbert L. Ho, Jeffrey P. Gambino | 2002-11-12 |
| 6458646 | Asymmetric gates for high density DRAM | Ramachandra Divakaruni, Wayne F. Ellis, Mary E. Weybright | 2002-10-01 |
| 6455886 | Structure and process for compact cell area in a stacked capacitor cell array | Ramachandra Divakaruni, Carl Radens | 2002-09-24 |
| 6452224 | Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby | Carl Radens | 2002-09-17 |
| 6451648 | Process for buried-strap self-aligned to deep storage trench | Ulrike Gruening, Carl Radens | 2002-09-17 |
| 6444548 | Bitline diffusion with halo for improved array threshold voltage control | Ramachandra Divakaruni, Yujun Li | 2002-09-03 |
| 6444516 | Semi-insulating diffusion barrier for low-resistivity gate conductors | Lawrence A. Clevenger, Rajarao Jammy, Oleg Gluschenkov, Irene McStay, Kwong Hon Wong +1 more | 2002-09-03 |
| 6440872 | Method for hybrid DRAM cell utilizing confined strap isolation | Ramachandra Divakaruni, Carl Radens, Stephan Kudelka | 2002-08-27 |
| 6441422 | Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well | Ramachandra Divakaruni, Carl Radens, Jai-Hoon Sim | 2002-08-27 |