Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7276775 | Intrinsic dual gate oxide MOSFET using a damascene gate process | Claude L. Bertin, John A. Fifield, John Jesse Higgins, Jack A. Mandelman, William R. Tonti +1 more | 2007-10-02 |
| 6531410 | Intrinsic dual gate oxide MOSFET using a damascene gate process | Claude L. Bertin, John A. Fifield, John Jesse Higgins, Jack A. Mandelman, William R. Tonti +1 more | 2003-03-11 |
| 5155572 | Vertical isolated-collector PNP transistor structure | Dominique Bonneau, Myriam Combes, Pierre Mollier, Seiki Ogura, Pascal Tannhof | 1992-10-13 |
| 4729006 | Sidewall spacers for CMOS circuit stress relief/isolation and method for making | Seiki Ogura, Jacob Riseman, Nivo Rovedo | 1988-03-01 |
| 4689113 | Process for forming planar chip-level wiring | Karanam Balasubramanyam, Jacob Riseman, Seiki Ogura | 1987-08-25 |