| 4944836 |
Chem-mech polishing method for producing coplanar metal/insulator films on a substrate |
Klaus D. Beyer, William L. Guthrie, Stanley R. Makarewicz, Eric Mendel, William J. Patrick +4 more |
1990-07-31 |
$17,895,000 |
| 4729006 |
Sidewall spacers for CMOS circuit stress relief/isolation and method for making |
Anthony J. Dally, Seiki Ogura, Nivo Rovedo |
1988-03-01 |
$29,571,000 |
| 4712125 |
Structure for contacting a narrow width PN junction region |
Harsaran S. Bhatia, Satyapal S. Bhatia, Emmanuel A. Valsamakis |
1987-12-08 |
$28,335,000 |
| 4689113 |
Process for forming planar chip-level wiring |
Karanam Balasubramanyam, Anthony J. Dally, Seiki Ogura |
1987-08-25 |
$31,388,000 |
| 4671851 |
Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique |
Klaus D. Beyer, James S. Makris, Eric Mendel, Karen A. Nummy, Seiki Ogura +1 more |
1987-06-09 |
$22,727,000 |
| 4648937 |
Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer |
Seiki Ogura, Nivo Rovedo, Ronald N. Schulz |
1987-03-10 |
$23,342,000 |
| 4641170 |
Self-aligned lateral bipolar transistors |
Seiki Ogura, Nivo Rovedo, Joseph F. Shepard, Jr. |
1987-02-03 |
$35,250,000 |
| 4583106 |
Fabrication methods for high performance lateral bipolar transistors |
Narasipur G. Anantha, Paul J. Tsang |
1986-04-15 |
$21,461,000 |
| 4551906 |
Method for making self-aligned lateral bipolar transistors |
Seiki Ogura, Nivo Rovedo, Joseph F. Shepard, Jr. |
1985-11-12 |
$10,728,000 |
| 4546536 |
Fabrication methods for high performance lateral bipolar transistors |
Narasipur G. Anantha, Paul J. Tsang |
1985-10-15 |
$20,804,000 |
| 4544576 |
Deep dielectric isolation by fused glass |
Wei-Kan Chu, William A. Pliskin |
1985-10-01 |
$19,725,000 |
| 4521952 |
Method of making integrated circuits using metal silicide contacts |
— |
1985-06-11 |
$37,017,000 |
| 4507171 |
Method for contacting a narrow width PN junction region |
Harsaran S. Bhatia, Satyapal S. Bhatia, Emmanuel A. Valsamakis |
1985-03-26 |
$18,335,000 |
| 4506435 |
Method for forming recessed isolated regions |
William A. Pliskin, Joseph F. Shepard, Jr. |
1985-03-26 |
$18,335,000 |
| 4492717 |
Method for forming a planarized integrated circuit |
William A. Pliskin |
1985-01-08 |
$24,317,000 |
| 4464212 |
Method for making high sheet resistivity resistors |
Harsaran S. Bhatia |
1984-08-07 |
$17,771,000 |
| 4462040 |
Single electrode U-MOSFET random access memory |
Irving T. Ho |
1984-07-24 |
$37,162,000 |
| 4419809 |
Fabrication process of sub-micrometer channel length MOSFETs |
Paul J. Tsang |
1983-12-13 |
$27,725,000 |
| 4419810 |
Self-aligned field effect transistor process |
— |
1983-12-13 |
$27,725,000 |
| 4356211 |
Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon |
— |
1982-10-26 |
$25,565,000 |
| 4252579 |
Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition |
Irving T. Ho |
1981-02-24 |
$24,710,000 |
| 4234362 |
Method for forming an insulator between layers of conductive material |
— |
1980-11-18 |
$42,876,000 |
| 4209349 |
Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
Irving T. Ho |
1980-06-24 |
$20,171,000 |
| 4209350 |
Method for forming diffusions having narrow dimensions utilizing reactive ion etching |
Irving T. Ho |
1980-06-24 |
$20,171,000 |
