Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4796069 | Schottky diode having limited area self-aligned guard ring and method for making same | Harsaran S. Bhatia, Santosh P. Gaur, John L. Mauer, IV | 1989-01-03 |
| 4691435 | Method for making Schottky diode having limited area self-aligned guard ring | Harsaran S. Bhatia, Santosh P. Gaur, John L. Mauer, IV | 1987-09-08 |
| 4583106 | Fabrication methods for high performance lateral bipolar transistors | Jacob Riseman, Paul J. Tsang | 1986-04-15 |
| 4546536 | Fabrication methods for high performance lateral bipolar transistors | Jacob Riseman, Paul J. Tsang | 1985-10-15 |
| 4510676 | Method of fabricating a lateral PNP transistor | Santosh P. Gaur, Yi-Shiou Huang, Paul J. Tsang | 1985-04-16 |
| 4492008 | Methods for making high performance lateral bipolar transistors | Tak H. Ning, Paul J. Tsang | 1985-01-08 |
| 4427989 | High density memory cell | Harsaran S. Bhatia, Santosh P. Gaur, James L. Walsh | 1984-01-24 |
| 4389281 | Method of planarizing silicon dioxide in semiconductor devices | Harsaran S. Bhatia, John S. Lechaton, James L. Walsh | 1983-06-21 |
| 4389294 | Method for avoiding residue on a vertical walled mesa | Harsaran S. Bhatia, John L. Mauer, IV, Homi G. Sarkary | 1983-06-21 |
| 4316319 | Method for making a high sheet resistance structure for high density integrated circuits | Augustine Wei-Chun Chang | 1982-02-23 |
| T101201 | Method for making stable nitride-defined Schottky barrier diodes | Harsaran S. Bhatia | 1981-11-03 |
| 4269631 | Selective epitaxy method using laser annealing for making filamentary transistors | Gurumakonda R. Srinivasan | 1981-05-26 |
| 4264382 | Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions | Harsaran S. Bhatia, Santosh P. Caur, Hans B. Pogge | 1981-04-28 |
| 4252581 | Selective epitaxy method for making filamentary pedestal transistor | Joseph R. Cavaliere, Richard R. Konian, Gurumakonda R. Srinivasan, Herbert I. Stoller, James L. Walsh | 1981-02-24 |
| 4252582 | Self aligned method for making bipolar transistor having minimum base to emitter contact spacing | Harsaran S. Bhatia, James L. Walsh | 1981-02-24 |
| 4236294 | High performance bipolar device and method for making same | Harsaran S. Bhatia, James L. Walsh | 1980-12-02 |
| 4228369 | Integrated circuit interconnection structure having precision terminating resistors | Robert A. Henle, James L. Walsh | 1980-10-14 |
| 4228450 | Buried high sheet resistance structure for high density integrated circuits with reach through contacts | Augustine Wei-Chun Chang | 1980-10-14 |
| 4214315 | Method for fabricating vertical NPN and PNP structures and the resulting product | Harsaran S. Bhatia, James L. Walsh | 1980-07-22 |
| 4196440 | Lateral PNP or NPN with a high gain | Harsaran S. Bhatia, Santosh P. Gaur, Hans B. Pogge | 1980-04-01 |