Issued Patents All Time
Showing 176–200 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6759292 | Method for fabricating a trench capacitor | Mihel Seitz, Michael P. Chudzik | 2004-07-06 |
| 6759291 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2004-07-06 |
| 6750097 | Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby | Ramachandra Divakaruni | 2004-06-15 |
| 6740920 | Vertical MOSFET with horizontally graded channel doping | Dureseti Chidambarrao, Kil-Ho Lee, Kevin McStay, Rajesh Rengarajan | 2004-05-25 |
| 6734056 | Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell | Dureseti Chidambarrao | 2004-05-11 |
| 6727539 | Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Larry Nesbit, Carl Radens | 2004-04-27 |
| 6727141 | DRAM having offset vertical transistors and method | Gary B. Bronner, Ramachandra Divakaruni, Byeong Y. Kim | 2004-04-27 |
| 6724088 | Quantum conductive barrier for contact to shallow diffusion region | Rajarao Jammy | 2004-04-20 |
| 6724031 | Method for preventing strap-to-strap punch through in vertical DRAMs | Hiroyuki Akatsu, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens | 2004-04-20 |
| 6724029 | Twin-cell flash memory structure and method | Louis L. Hsu, Chung H. Lam, Carl Radens, William R. Tonti | 2004-04-20 |
| 6720602 | Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of producing the same | Lawrence A. Clevenger, Louis L. Hsu, Carl Radens | 2004-04-13 |
| 6720213 | Low-K gate spacers by fluorine implantation | Jeffrey P. Gambino, William R. Tonti | 2004-04-13 |
| 6709926 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy | 2004-03-23 |
| 6707095 | Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation | Dureseti Chidambarrao, Carl Radens | 2004-03-16 |
| 6703274 | Buried strap with limited outdiffusion and vertical transistor DRAM | Dureseti Chidambarrao, Ramachandra Divakaruni, Raymond Van Roijen | 2004-03-09 |
| 6693041 | Self-aligned STI for narrow trenches | Ramachandra Divakaruni, Carl Radens | 2004-02-17 |
| 6674134 | Structure and method for dual gate oxidation for CMOS technology | Wayne S. Berry, Jeffrey P. Gambino, William R. Tonti | 2004-01-06 |
| 6674139 | Inverse T-gate structure using damascene processing | Carl Radens, William R. Tonti | 2004-01-06 |
| 6670667 | Asymmetric gates for high density DRAM | Ramachandra Divakaruni, Wayne F. Ellis, Mary E. Weybright | 2003-12-30 |
| 6664161 | Method and structure for salicide trench capacitor plate electrode | Michael P. Chudzik, Carl Radens, Rajarao Jammy, Kenneth T. Settlemyer, Jr., Padraic Shafer +1 more | 2003-12-16 |
| 6656807 | Grooved planar DRAM transfer device using buried pocket | Gary B. Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak | 2003-12-02 |
| 6653678 | Reduction of polysilicon stress in trench capacitors | Dureseti Chidambarrao, Rajarao Jammy | 2003-11-25 |
| 6649935 | Self-aligned, planarized thin-film transistors, devices employing the same | Louis L. Hsu, William R. Tonti, Li-Kong Wang | 2003-11-18 |
| 6646949 | Word line driver for dynamic random access memories | Wayne F. Ellis, Louis L. Hsu, William R. Tonti | 2003-11-11 |
| 6642566 | Asymmetric inside spacer for vertical transistor | Ramachandra Divakaruni, Haining Yang | 2003-11-04 |