BD

Bijan Davari

IBM: 19 patents #5,782 of 70,183Top 9%
GE: 2 patents #13,562 of 36,430Top 40%
RI Rensselaer Polytechnic Institute: 1 patents #306 of 819Top 40%
UF US Air Force: 1 patents #6,190 of 16,312Top 40%
Overall (All Time): #180,231 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12019701 Computer architecture for string searching Octavian Popescu, Vadim Sheinin, Gheorghe Almasi 2024-06-25
11907766 Shared enterprise cloud Dinesh C. Verma, Raghu Kiran Ganti 2024-02-20
11907963 On-device privacy-preservation and personalization Kelvin Kakugwa, Joe Latone, Nirmit V. Desai, Shahrokh Daijavad, Wendy Chong +2 more 2024-02-20
11803413 Migrating complex legacy applications Dinesh C. Verma, Shahrokh Daijavad 2023-10-31
10085157 Reconfiguring a mobile network based on cellular network state information Shahrokh Daijavad, Brian P. Naughton, Dinesh C. Verma 2018-09-25
9838108 IP based real-time communications over a mobile network Shahrokh Daijavad, Brian P. Naughton, Dinesh C. Verma 2017-12-05
7974826 Energy system modeling apparatus and methods Scott Williams, Peter Pechtl, Larry Keith McDonald, Alfred Ong'iro 2011-07-05
7356383 Methods and apparatus for optimizing combined cycle/combined process facilities Peter Pechtl, Martin Posch, Marco Robert Dieleman 2008-04-08
6800518 Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering Robert E. Bendernagel, Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi +1 more 2004-10-05
6756257 Patterned SOI regions on semiconductor chips Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari 2004-06-29
6566177 Silicon-on-insulator vertical array device trench capacitor DRAM Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Jack A. Mandelman, Dan Moy +3 more 2003-05-20
6426252 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Jack A. Mandelman, Dan Moy +3 more 2002-07-30
6337253 Process of making buried capacitor for silicon-on-insulator structure Effendi Leobandung, Werner Rausch, Ghavam G. Shahidi 2002-01-08
6333532 Patterned SOI regions in semiconductor chips Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari 2001-12-25
6188122 Buried capacitor for silicon-on-insulator structure Effendi Leobandung, Werner Rausch, Ghavam G. Shahidi 2001-02-13
6087199 Method for fabricating a very dense chip package H. Bernhard Pogge, Johann Greschner, Howard L. Kalter 2000-07-11
5998868 Very dense chip package H. Bernhard Pogge, Johann Greschner, Howard L. Kalter 1999-12-07
5784311 Two-device memory cell on SOI for merged logic and memory applications Fariborz Assaderaghi, Louis L. Hsu, Jack A. Mandelman, Ghavam G. Shahidi 1998-07-21
5541427 SRAM cell with capacitor Barbara A. Chappell, George A. Sai-Halasz, Yuan Taur 1996-07-30
4889819 Method for fabricating shallow junctions by preamorphizing with dopant of same conductivity as substrate Eti Ganin, David L. Harame, George A. Sai-Halasz 1989-12-26
4881105 Integrated trench-transistor structure and fabrication process Wei Hwang, Nicky C. Lu 1989-11-14
4621233 Non-destructive testing of semiconductors using acoustic wave method Pankaj K. Das 1986-11-04
4569728 Selective anodic oxidation of semiconductors for pattern generation Pankaj K. Das 1986-02-11