Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907717 | Techniques for efficiently transferring data to a processor | Andrew Kerr, Jack Choquette, Omkar Paranjape, Poornachandra Rao, Shirish Gadre +4 more | 2024-02-20 |
| 11803380 | High performance synchronization mechanisms for coordinating operations on a computer system | Olivier Giroux, Jack Choquette, Ronny Meir Krashinsky, Steve HEINRICH, Shirish Gadre | 2023-10-31 |
| 11604649 | Techniques for efficiently transferring data to a processor | Andrew Kerr, Jack Choquette, Omkar Paranjape, Poornachandra Rao, Shirish Gadre +4 more | 2023-03-14 |
| 11347668 | Unified cache for diverse memory traffic | Ronny Meir Krashinsky, Steven James Heinrich, Shirish Gadre, John H. Edmondson, Jack Choquette +5 more | 2022-05-31 |
| 11080051 | Techniques for efficiently transferring data to a processor | Andrew Kerr, Jack Choquette, Omkar Paranjape, Poornachandra Rao, Shirish Gadre +4 more | 2021-08-03 |
| 10705994 | Unified cache for diverse memory traffic | Ronny Meir Krashinsky, Steven James Heinrich, Shirish Gadre, John H. Edmondson, Jack Choquette +5 more | 2020-07-07 |
| 10489200 | Hierarchical staging areas for scheduling threads for execution | Olivier Giroux, Jack Choquette, Robert J. Stoll, Michael A. Fetterman | 2019-11-26 |
| 10459861 | Unified cache for diverse memory traffic | Ronny Meir Krashinsky, Steven James Heinrich, Shirish Gadre, John H. Edmondson, Jack Choquette +5 more | 2019-10-29 |
| 10255228 | System and method for performing shaped memory access operations | Jack Choquette, Manuel Gautho, Ming Y. Siu | 2019-04-09 |
| 9971699 | Method to control cache replacement for decoupled data fetch | Ronny Meir Krashinsky | 2018-05-15 |
| 9830158 | Speculative execution and rollback | Jack Choquette, Olivier Giroux, Robert J. Stoll | 2017-11-28 |
| 9798544 | Reordering buffer for memory access locality | Olivier Giroux, Jack Choquette, Robert J. Stoll | 2017-10-24 |
| 9626191 | Shaped register file reads | Jack Choquette, Michael A. Fetterman, Shirish Gadre, Omkar Paranjape, Anjana Rajendran +4 more | 2017-04-18 |
| 9612836 | System, method, and computer program product for implementing software-based scoreboarding | Robert Ohannessian, Michael A. Fetterman, Olivier Giroux, Jack Choquette, Shirish Gadre +1 more | 2017-04-04 |
| 9606808 | Method and system for resolving thread divergences | Jack Choquette, Jeff Tuckey, Michael Siu, Robert J. Stoll, Olivier Giroux | 2017-03-28 |
| 9477482 | System, method, and computer program product for implementing multi-cycle register file bypass | Ian Kwong, Ming Y. Siu, Jack Choquette, Michael A. Fetterman | 2016-10-25 |
| 9471307 | System and processor that include an implementation of decoupled pipelines | Olivier Giroux, Michael A. Fetterman, Robert Ohannessian, Shirish Gadre, Jack Choquette +2 more | 2016-10-18 |
| 8533435 | Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict | Ming Y. Siu, Yan Yan Tang, John Erik Lindholm, Michael C. Shebanow, Stuart F. Oberman | 2013-09-10 |
| 8321761 | ECC bits used as additional register file storage | Fred Gruner, Yan Yan Tang | 2012-11-27 |
| 8250439 | ECC bits used as additional register file storage | Fred Gruner | 2012-08-21 |
| 7509643 | Method and apparatus for supporting asymmetric multi-threading in a computer system | Si-En Chang | 2009-03-24 |
| 7484039 | Method and apparatus for implementing a grid storage system | Ningchuan Shen | 2009-01-27 |
| 7188324 | Assertion morphing in functional verification of integrated circuit design | Si-En Chang | 2007-03-06 |