Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10289469 | Reliability enhancement utilizing speculative execution systems and methods | Nick Fortino, Ben Hertzberg | 2019-05-14 |
| 9734545 | Software methods in a GPU | Jerome F. Duluk, Jr., John Christopher Cook, Gregory Scott Palmer | 2017-08-15 |
| 9490847 | Error detection and correction for external DRAM | Shane J. Keil, John S. Montrym | 2016-11-08 |
| 8321761 | ECC bits used as additional register file storage | Xiaogang Qiu, Yan Yan Tang | 2012-11-27 |
| 8301980 | Error detection and correction for external DRAM | Shane J. Keil, John S. Montrym | 2012-10-30 |
| 8250439 | ECC bits used as additional register file storage | Xiaogang Qiu | 2012-08-21 |
| 8190974 | Error detection and correction for external DRAM | Shane J. Keil, John S. Montrym | 2012-05-29 |
| 7813364 | Cross-bar switch incorporating a sink port with retry capability | Abbas Rashid, Nazar Zaidi, Mark Bryers | 2010-10-12 |
| 7733905 | Cross-bar switch having bandwidth allocation | Abbas Rashid, Nazar Zaidi, Mark Bryers | 2010-06-08 |
| 7213129 | Method and system for a two stage pipelined instruction decode and alignment using previous instruction length | Mike Morrison, Kushagra Vaid | 2007-05-01 |
| 7170902 | Cross-bar switch incorporating a sink port with retry capability | Abbas Rashid, Nazar Zaidi, Mark Bryers | 2007-01-30 |
| 7123585 | Cross-bar switch with bandwidth allocation | Abbas Rashid, Nazar Zaidi, Mark Bryers | 2006-10-17 |
| 7068603 | Cross-bar switch | Abbas Rashid, Nazar Zaidi, Mark Bryers | 2006-06-27 |
| 6920529 | Transferring data between cache memory and a media access controller | Robert Hathaway, Ricardo Ramirez | 2005-07-19 |
| 6901489 | Streaming input engine facilitating data transfers between application engines and memory | Ricardo Ramirez | 2005-05-31 |
| 6901482 | Managing ownership of a full cache line using a store-create operation | David T. Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Nazar Zaidi | 2005-05-31 |
| 6901488 | Compute engine employing a coprocessor | Robert Hathaway, Ricardo Ramirez | 2005-05-31 |
| 6880049 | Sharing a second tier cache memory in a multi-processor | David T. Hass, Ramesh Panwar, Nazar Zaidi | 2005-04-12 |
| 6862669 | First tier cache memory preventing stale data storage | David T. Hass, Robert Hathaway | 2005-03-01 |
| 6839808 | Processing cluster having multiple compute engines and shared tier one caches | David T. Hass, Robert Hathaway, Ramesh Penwar, Ricardo Ramirez, Nazar Zaidi | 2005-01-04 |
| 6754774 | Streaming output engine facilitating data transfers between application engines and memory | Ricardo Ramirez | 2004-06-22 |
| 6684322 | Method and system for instruction length decode | Mike Morrison, Kushagra Vaid | 2004-01-27 |
| 6032278 | Method and apparatus for performing scan testing | Praveen Parvathala | 2000-02-29 |
| 5978944 | Method and apparatus for scan testing dynamic circuits | Praveen Parvathala | 1999-11-02 |
| 5872795 | Method and apparatus for scan testing of multi-phase logic | Praveen Parvathala | 1999-02-16 |