Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MT

Mark R. Taylor — 16 Patents

IBM: 11 patents #10,022 of 70,183Top 15%
FLFinsbury (Development) Limited: 1 patents #8 of 15Top 55%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
UNUnknown: 1 patents #29,356 of 83,584Top 40%
JDJohn Deere: 1 patents #2,985 of 5,518Top 55%
South Burlington, VT: #142 of 1,136 inventorsTop 15%
Vermont: #478 of 4,968 inventorsTop 10%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Mark R. Taylor has been granted 16 US patents while listed as an inventor at IBM. The first was granted in 1993 and the most recent in October 2019. Mark R. Taylor ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Mark R. Taylor in South Burlington, VT, US.

Patents per Year

Patents granted per year, 1993 to 2019Bar chart with a peak of 5 patents in 2010.peak 51993: 1 patents19931996: 1 patents2000: 1 patents20002004: 1 patents2005: 1 patents20052007: 2 patents2008: 1 patents20082009: 1 patents2010: 5 patents20102013: 1 patents2019: 1 patents2019

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10436837 Auto test grouping/clock sequencing for at-speed test Hardik Bhagat, Baalaji Konda Ramamoorthy, Douglas E. Sprague, Greeshma Jayakumar 2019-10-08 $23,319,000
8538718 Clock edge grouping for at-speed test Gary D. Grise, Vikram Iyengar, Douglas E. Sprague 2013-09-17 $4,204,000
7779375 Design structure for shutting off data capture across asynchronous clock domains during at-speed testing Gary D. Grise, Vikram Iyengar 2010-08-17 $4,695,000
7734968 Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit) Richard J. Grupp, Kelly A. Ockunzzi 2010-06-08 $3,517,000
7721170 Apparatus and method for selectively implementing launch off scan capability in at speed testing Gary D. Grise, Vikram Iyengar, David E. Lackey 2010-05-18 $4,666,000
7685542 Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing Gary D. Grise, Vikram Iyengar 2010-03-23 $4,775,000
7659740 System and method of digitally testing an analog driver circuit Joseph O. Marsh, Jeremy K. Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu +2 more 2010-02-09 $5,437,000
7497876 Prosthetic implant Michael Antony Tuke, Andrew Clive Taylor, Peter Thomsen 2009-03-03
7466156 System of digitally testing an analog driver circuit Joseph O. Marsh, Jeremy K. Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu +2 more 2008-12-16 $6,236,000
7308630 Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit) Richard J. Grupp, Kelly A. Ockunzzi 2007-12-11 $7,826,000
7240266 Clock control circuit for test that facilitates an at speed structural test Henry R. Farmer, Gary D. Grise, David W. Milton 2007-07-03 $6,885,000
6882159 Associated grouping of embedded cores for manufacturing test Bruce Cowan, Kelly A. Ockunzzi, Jessica H. Pratt 2005-04-19 $7,105,000
6804803 Method for testing integrated logic circuits Carl Barnhart, Robert W. Bassett, Brion Keller, David E. Lackey, Donald L. Wheater 2004-10-12 $7,244,000
6016646 Adjustable, resilent twine guide finger for twine wrap mechanism of large round baler Roger William Frimml, Henry D. Anstey 2000-01-25 $51,105,000
5519975 Drainage roofing tile Laura B. Taylor 1996-05-28
5248930 Wheel wall electrostatic generator 1993-09-28