Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11335657 | Wafer scale supercomputer | Evan G. Colgan, Timothy J. Chainer, Kai Schleupen, Diego Anzola, Mark D. Schultz +1 more | 2022-05-17 |
| 10169288 | Node interconnect architecture to implement high-performance supercomputer | Evan G. Colgan, Daniel M. Kuchta | 2019-01-01 |
| 10171105 | Carry-less population count | Deepak Singh, Brian M. Rogers | 2019-01-01 |
| 9953501 | Methods of forming microelectronic smart tags | Paul S. Andry, John U. Knickerbocker, Robert L. Wisnieff | 2018-04-24 |
| 9684862 | Microelectronic smart tags | Paul S. Andry, John U. Knickerbocker, Robert L. Wisnieff | 2017-06-20 |
| 9568960 | Supercomputer using wafer scale integration | Evan G. Colgan, John U. Knickerbocker | 2017-02-14 |
| 9348791 | N × N connector for optical bundles of transmit / receive duplex pairs to implement supercomputer | Evan G. Colgan, Daniel M. Kuchta | 2016-05-24 |
| 8954712 | Computer system including an all-to-all communication network of processors connected using electrical and optical links | Evan G. Colgan, Daniel M. Kuchta | 2015-02-10 |
| 8569874 | High memory density, high input/output bandwidth logic-memory structure and architecture | Evan G. Colgan, Sampath Purushothaman, Klmberley A. Kelly, Roy R. Yu | 2013-10-29 |
| 8429107 | System for address-event-representation network simulation | Daniel J. Friedman, Ralph Linsker, Mark B. Ritter | 2013-04-23 |
| 8176362 | Online multiprocessor system reliability defect testing | Vikram Iyengar, Phillip J. Nigh | 2012-05-08 |
| 7676588 | Programmable network protocol handler architecture | Christos J. Georgiou | 2010-03-09 |
| 7477608 | Methods for routing packets on a linear array of processors | Peter Hochschild, Richard A. Swetz, Henry S. Warren, Jr. | 2009-01-13 |
| 7203790 | Flexible techniques for associating cache memories with processors and main memory | Peter Hochschild, Henry S. Warren, Jr. | 2007-04-10 |
| 7072970 | Programmable network protocol handler architecture | Christos J. Georgiou, Valentina Salapura, Robert M. Bunce | 2006-07-04 |
| 6961782 | Methods for routing packets on a linear array of processors | Peter Hochschild, Richard A. Swetz, Henry S. Warren, Jr. | 2005-11-01 |
| 6961804 | Flexible techniques for associating cache memories with processors and main memory | Peter Hochschild, Henry S. Warren, Jr. | 2005-11-01 |
| 6836015 | Optical assemblies for transmitting and manipulating optical beams | Dinesh Gupta, Lisa J. Jimarez, Steven P. Ostrander, Brenda Peterson, Mark V. Pierson +2 more | 2004-12-28 |
| 6384833 | Method and parallelizing geometric processing in a graphics rendering pipeline | Peter Hochschild, Henry S. Warren, Jr. | 2002-05-07 |
| 5805589 | Central shared queue based time multiplexed packet switch with deadlock avoidance | Peter Hochschild | 1998-09-08 |
| 5566342 | Scalable switch wiring technique for large arrays of processors | Donald G. Grice, Peter Hochschild, Craig Brian Stunkel | 1996-10-15 |
| 5546391 | Central shared queue based time multiplexed packet switch with deadlock avoidance | Peter Hochschild | 1996-08-13 |
| 5414740 | Synchronous communication system having multiplexed information transfer and transition phases | Bruce D. Gavril, Peter Hochschild, Craig Brian Stunkel | 1995-05-09 |
| 5414832 | Tunable synchronous electronic communication apparatus | Bruce D. Gavril, Peter Hochschild, Craig Brian Stunkel | 1995-05-09 |
| 5371733 | Method and apparatus for centralized determination of virtual transmission delays in networks of counter-synchronized communication devices | Bruce D. Gavril, Peter Hochschild, Craig Brian Stunkel | 1994-12-06 |