Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11165719 | Network architecture with locally enhanced bandwidth | Philip Heidelberger | 2021-11-02 |
| 10425358 | Network switch architecture supporting multiple simultaneous collective operations | Dong Chen, Philip Heidelberger | 2019-09-24 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +55 more | 2015-07-14 |
| 8811378 | Dual network types solution for computer interconnects | Alan F. Benner, Ramakrishnan Rajamony, Eugen Schenfeld, Peter Walker | 2014-08-19 |
| 8194638 | Dual network types solution for computer interconnects | Alan F. Benner, Ramakrishnan Rajamony, Eugen Schenfeld, Peter Walker | 2012-06-05 |
| 7724733 | Interconnecting network for switching data packets and method for switching data packets | Alan F. Benner, Cyriel Minkenberg | 2010-05-25 |
| 7187688 | Priority arbitration mechanism | Derrick LeRoy Garmire, Jay R. Herring | 2007-03-06 |
| 6542502 | Multicasting using a wormhole routing switching element | Jay R. Herring, Rajeev Sivaram | 2003-04-01 |
| 6031835 | Method for deadlock free and and reliable routing in a packet switched network | Bulent Abali, Kevin J. Reilly | 2000-02-29 |
| 6003091 | Verifying a time-of-day counter | Robert Francis Bartfai, Derrick LeRoy Garmire, Jay R. Herring, Francis A. Kampf, Nicholas P. Rash +1 more | 1999-12-14 |
| 5925107 | Verifying a time-of-day counter | Robert Francis Bartfai, Derrick LeRoy Garmire, Jay R. Herring, Francis A. Kampf, Nicholas P. Rash +1 more | 1999-07-20 |
| 5721820 | System for adaptively routing data in switching network wherein source node generates routing message identifying one or more routes form switch selects | Bulent Abali | 1998-02-24 |
| 5566342 | Scalable switch wiring technique for large arrays of processors | Monty M. Denneau, Donald G. Grice, Peter Hochschild | 1996-10-15 |
| 5453978 | Technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch | Harish Sethu, Robert Frederick Stucke | 1995-09-26 |
| 5414832 | Tunable synchronous electronic communication apparatus | Monty M. Denneau, Bruce D. Gavril, Peter Hochschild | 1995-05-09 |
| 5414740 | Synchronous communication system having multiplexed information transfer and transition phases | Monty M. Denneau, Bruce D. Gavril, Peter Hochschild | 1995-05-09 |
| 5371733 | Method and apparatus for centralized determination of virtual transmission delays in networks of counter-synchronized communication devices | Monty M. Denneau, Bruce D. Gavril, Peter Hochschild | 1994-12-06 |
| 5371735 | Communication network with non-unique device identifiers and method of establishing connection paths in such a network | Monty M. Denneau, Peter Hochschild | 1994-12-06 |