Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12026584 | Optically multiplexed quantum control interface | Jason S. Orcutt, Patryk Gumann | 2024-07-02 |
| 11812673 | Quantum device with modular quantum building blocks | Salvatore Bernardo Olivadese | 2023-11-07 |
| 11308390 | Methods and systems of neuron leaky integrate and fire circuits | Takeo Yasuda | 2022-04-19 |
| 11201686 | Optically multiplexed quantum control | Jason S. Orcutt, Patryk Gumann | 2021-12-14 |
| 10971672 | Quantum device with modular quantum building blocks | Salvatore Bernardo Olivadese | 2021-04-06 |
| 10671911 | Current mirror scheme for an integrating neuron circuit | Takeo Yasuda | 2020-06-02 |
| 10643125 | Methods and systems of neuron leaky integrate and fire circuits | Takeo Yasuda | 2020-05-05 |
| 9793913 | Single-flux-quantum probabilistic digitizer | John F. Bulzacchelli, Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky | 2017-10-17 |
| 9614532 | Single-flux-quantum probabilistic digitizer | John F. Bulzacchelli, Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky | 2017-04-04 |
| 9203022 | Resistive random access memory devices with extremely reactive contacts | Marinus Hopstaken, Jeehwan Kim, Seyoung Kim | 2015-12-01 |
| 8949685 | Soft error protection in individual memory devices | Douglas J. Joseph, Jose A. Tierno | 2015-02-03 |
| 8832010 | Electronic synapses from stochastic binary memory devices | Bipin Rajendran | 2014-09-09 |
| 8832011 | Electronic synapses from stochastic binary memory devices | Bipin Rajendran | 2014-09-09 |
| 8429107 | System for address-event-representation network simulation | Monty M. Denneau, Daniel J. Friedman, Ralph Linsker | 2013-04-23 |
| 8161314 | Method and system for analog frequency clocking in processor cores | Lawrence Jacobowitz, Daniel J. Stigliani, Jr. | 2012-04-17 |
| 8053819 | Three-dimensional cascaded power distribution in a semiconductor device | Kerry Bernstein, Paul W. Coteus, Philip G. Emma, Allan M. Hartstein, Stephen V. Kosonocky +1 more | 2011-11-08 |
| 7917785 | Method of optimizing performance of multi-core chips and corresponding circuit and computer program product | Lawrence Jacobowitz, Daniel J. Stigliani, Jr. | 2011-03-29 |
| 7917799 | Method and system for digital frequency clocking in processor cores | Lawrence Jacobowitz, Daniel J. Stigliani, Jr. | 2011-03-29 |
| 7913202 | Wafer level I/O test, repair and/or customization enabled by I/O layer | Kerry Bernstein, Paul W. Coteus, Ibrahim M. Elfadel, Philip G. Emma, Daniel J. Friedman +3 more | 2011-03-22 |
| 7721182 | Soft error protection in individual memory devices | Douglas J. Joseph, Jose A. Tierno | 2010-05-18 |
| 7720386 | Impedance matching circuit with simultaneous shielding of parasitic effects for transceiver modules | Daniel M. Kuchta, Albert E. Ruehli, Christian Schuster | 2010-05-18 |
| 7521950 | Wafer level I/O test and repair enabled by I/O layer | Kerry Bernstein, Paul W. Coteus, Ibrahim M. Elfadel, Philip G. Emma, Daniel J. Friedman +3 more | 2009-04-21 |
| 7509053 | Impedance matching circuit with simultaneous shielding of parasitic effects for transceiver modules | Daniel M. Kuchta, Albert E. Ruehli, Christian Schuster | 2009-03-24 |
| 7412172 | Impedance matching circuit with simultaneous shielding of parasitic effects for transceiver modules | Daniel M. Kuchta, Albert E. Ruehli, Christian Schuster | 2008-08-12 |
| 7402854 | Three-dimensional cascaded power distribution in a semiconductor device | Kerry Bernstein, Paul W. Coteus, Philip G. Emma, Allan M. Hartstein, Stephen V. Kosonocky +1 more | 2008-07-22 |