Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8421495 | Speed binning for dynamic and adaptive power control | Theodoros E. Anemikos, Nazmul Habib, Susan K. Lichtensteiger | 2013-04-16 |
| 8418090 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jason D. Hibbeler, Juergen Koehl | 2013-04-09 |
| 8302063 | Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression | Umberto Garofano, James E. Jasmin, Ivan L. Wemple, Tad J. Wilder | 2012-10-30 |
| 8234594 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Markus Buehler, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak | 2012-07-31 |
| 8136066 | Apparatus and computer program product for semiconductor yield estimation | Jason D. Hibbeler, Juergen Koehl, William J. Livingstone, Daniel N. Maynard | 2012-03-13 |
| 8132129 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jason D. Hibbeler, Juergen Koehl | 2012-03-06 |
| 8095907 | Reliability evaluation and system fail warning methods using on chip parametric monitors | John R. Goss, Nazmul Habib, Robert McMahon | 2012-01-10 |
| 8010916 | Test yield estimate for semiconductor products created from a library | Markus Buehler, Jason D. Hibbeler, Juergen Koehl | 2011-08-30 |
| 7996808 | Computer readable medium, system and associated method for designing integrated circuits with loop insertions | Andreas H. A. Arp, Markus Buehler, Juergen Koehl, Philipp Salz | 2011-08-09 |
| 7984394 | Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Markus Buehler, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak | 2011-07-19 |
| 7960836 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Markus Buehler, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak | 2011-06-14 |
| 7917451 | Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screens | Thomas S. Barnett, Nazmul Habib, Susan K. Lichtensteiger, Raymond J. Rosner | 2011-03-29 |
| 7810054 | Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point | Theodoros E. Anemikos, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson | 2010-10-05 |
| 7656182 | Testing method using a scalable parametric measurement macro | John R. Goss, Nazmul Habib, Robert McMahon | 2010-02-02 |
| 7560946 | Method of acceptance for semiconductor devices | John R. Goss, Nazmul Habib, Robert McMahon | 2009-07-14 |
| 7496874 | Semiconductor yield estimation | Jason D. Hibbeler, Juergen Koehl, William J. Livingstone, Daniel Nelson Mayuard | 2009-02-24 |
| 7487477 | Parametric-based semiconductor design | John R. Goss, Nazmul Habib, Robert McMahon | 2009-02-03 |
| 7487476 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jason D. Hibbeler, Juergen Koehl | 2009-02-03 |
| 7477961 | Equivalent gate count yield estimation for integrated circuit devices | Thomas S. Barnett, William Y. Chang, Rashmi D. Chatty, Sebnem Jaji, Kerry A. Kravec +4 more | 2009-01-13 |
| 7398485 | Yield optimization in router for systematic defects | Markus Buehler, Jason D. Hibbeler, Juergen Koehl, Daniel N. Maynard | 2008-07-08 |
| 7386815 | Test yield estimate for semiconductor products created from a library | Markus Buehler, Jason D. Hibbeler, Juergen Koehl | 2008-06-10 |
| 7380233 | Method of facilitating integrated circuit design using manufactured property values | Steven M Fox, Donald J. Hathaway, Ian P. Stobert | 2008-05-27 |
| 7089132 | Method and system for providing quality control on wafers running on a manufacturing line | Vernon R. Norman, Michael R. Ouellette, Mark S. Styduhar, Brian Worth | 2006-08-08 |
| 7013441 | Method for modeling integrated circuit yield | Edward K. Evans, Sean Horner, Raymond J. Rosner, Andrew S. Wienick, Joseph W. Yoder | 2006-03-14 |