JB

Jeanne P. Bickford

IBM: 52 patents #1,616 of 70,183Top 3%
Globalfoundries: 21 patents #139 of 4,424Top 4%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
📍 South Burlington, VT: #21 of 1,136 inventorsTop 2%
🗺 Vermont: #77 of 4,968 inventorsTop 2%
Overall (All Time): #26,499 of 4,157,543Top 1%
74
Patents All Time

Issued Patents All Time

Showing 26–50 of 74 patents

Patent #TitleCo-InventorsDate
9262569 Balancing sensitivities with respect to timing closure for integrated circuits Eric A. Foreman, David J. Hathaway 2016-02-16
9171125 Limiting skew between different device types to meet performance requirements of an integrated circuit Igor Arsovski, Mark W. Kuemerle 2015-10-27
9157956 Adaptive power control using timing canonicals Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Clarence R. Ogilvie, Tad J. Wilder +1 more 2015-10-13
9152168 Systems and methods for system power estimation Rebecca A. Bickford, Susan K. Lichtensteiger, Jeanne H. Raymond 2015-10-06
9104834 Systems and methods for single cell product path delay analysis Peter A. Habitz, Vikram Iyengar, Brian Worth, Jinjun Xiong 2015-08-11
9064087 Semiconductor device reliability model and methodologies for use thereof Nazmul Habib, Baozhen Li, Pascal A. Nsame 2015-06-23
9058034 Integrated circuit product yield optimization using the results of performance path testing Peter A. Habitz, Vikram Iyengar, Jinjun Xiong 2015-06-16
8963620 Controlling circuit voltage and frequency based upon location-dependent temperature Eric A. Foreman, David J. Hathaway, Mark W. Kuemerle, Susan K. Lichtensteiger 2015-02-24
8938701 Method of managing electro migration in logic designs and design structure thereof John E. Barwin 2015-01-20
8904329 Systems and methods for single cell product path delay analysis Peter A. Habitz, Vikram Iyengar, Brian Worth, Jinjun Xiong 2014-12-02
8850380 Selective voltage binning within a three-dimensional integrated chip stack Eric A. Foreman 2014-09-30
8843874 Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger 2014-09-23
8839165 Power/performance optimization through continuously variable temperature-based voltage control Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger 2014-09-16
8839170 Power/performance optimization through temperature/voltage control Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger 2014-09-16
8839177 Method and system allowing for semiconductor design rule optimization Mark D. Aubel, Howard S. Landis, Michael Ross, Mark S. Styduhar, Charles H. Windisch, Jr. 2014-09-16
8799836 Yield optimization for design library elements at library element level or at product level Anand Kumaraswamy, Terry M. Lowe, Mark S. Styduhar, Lijiang Wang 2014-08-05
8719763 Frequency selection with selective voltage binning Eric A. Foreman, Vladimir Zolotov 2014-05-06
8631375 Via selection in integrated circuit design Robert R. Arelt, Andrew D. Huber, Gustavo E. Tellez, Karl W. Vinson, Tina Wagner 2014-01-14
8578314 Circuit design with growable capacitor arrays Gerald P. Pomichter, Jr., Mark S. Styduhar, Bernhard J. Wunder 2013-11-05
8560990 Method of managing electro migration in logic designs and design structure thereof John E. Barwin 2013-10-15
8543960 Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger 2013-09-24
8543966 Test path selection and test program generation for performance testing integrated circuit chips Peter A. Habitz, Vikram Iyengar, David E. Lackey, Jinjun Xiong 2013-09-24
8539429 System yield optimization using the results of integrated circuit chip performance path testing Peter A. Habitz, Vikram Iyengar 2013-09-17
8490040 Disposition of integrated circuits using performance sort ring oscillator and performance path testing Peter A. Habitz, Vikram Iyengar, David E. Lackey, Jinjun Xiong 2013-07-16
8423945 Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes Allan O. Cruz, Michelle Lynn GILL, Howard S. Landis, David V. MacDonnell, II, Donald J. Samuels +1 more 2013-04-16