Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7381986 | Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer | Brion Keller, Bernd K. F. Koenermann, Donald L. Wheater | 2008-06-03 |
| 7131074 | Nested voltage island architecture | Thomas R. Bednar, Scott Whitney Gould, Douglas W. Stout, Paul S. Zuchowski | 2006-10-31 |
| 6883152 | Voltage island chip implementation | Thomas R. Bednar, Scott Whitney Gould, Douglas W. Stout, Paul S. Zuchowski | 2005-04-19 |
| 6865723 | Method for insertion of test points into integrated logic circuit designs | — | 2005-03-08 |
| 6856270 | Pipeline array | Henry R. Farmer, Steven F. Oakland | 2005-02-15 |
| 6820240 | Voltage island chip implementation | Thomas R. Bednar, Scott Whitney Gould, Douglas W. Stout, Paul S. Zuchowski | 2004-11-16 |
| 6804803 | Method for testing integrated logic circuits | Carl Barnhart, Robert W. Bassett, Brion Keller, Mark R. Taylor, Donald L. Wheater | 2004-10-12 |
| 6792582 | Concurrent logical and physical construction of voltage islands for mixed supply voltage designs | John M. Cohn, Alvar A. Dean, David J. Hathaway, Thomas Lepsic, Susan K. Lichtensteiger +2 more | 2004-09-14 |
| 6779163 | Voltage island design planning | Thomas R. Bednar, Scott Whitney Gould, Douglas W. Stout, Paul S. Zuchowski | 2004-08-17 |
| 6745373 | Method for insertion of test points into integrated circuit logic designs | — | 2004-06-01 |
| 6731154 | Global voltage buffer for voltage islands | Thomas R. Bednar, Scott Whitney Gould, Douglas W. Stout, Paul S. Zuchowski | 2004-05-04 |
| 6636995 | Method of automatic latch insertion for testing application specific integrated circuits | Alvar A. Dean, Joseph A. Iadanza, Sebastian T. Ventrone | 2003-10-21 |
| 6609228 | Latch clustering for power optimization | Paul H. Bergeron, Keith M. Carrig, Alvar A. Dean, Roger P. Gregor, David J. Hathaway +2 more | 2003-08-19 |
| 6577156 | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox | Darren L. Anand, John E. Barth, Jr., John A. Fifield, Pamela S. Gillis, Peter O. Jakobsen +4 more | 2003-06-10 |
| 6567943 | D flip-flop structure with flush path for high-speed boundary scan applications | Carl Barnhart, Steven F. Oakland | 2003-05-20 |
| 6566681 | Apparatus for assisting backside focused ion beam device modification | Theodore M. Levin, Leah Pastel | 2003-05-20 |
| 6467044 | On-board clock-control templates for testing integrated circuits | — | 2002-10-15 |
| 6300809 | Double-edge-triggered flip-flop providing two data transitions per clock cycle | Roger P. Gregor, David J. Hathaway, Steven F. Oakland | 2001-10-09 |
| 5783960 | Integrated circuit device with improved clock signal control | — | 1998-07-21 |
| 5146460 | Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility | Dennis F. Ackerman, David R. Bender, Salina Sau-Yue Chu, George R. Deibert, Gary G. Hallock +2 more | 1992-09-08 |