PH

Peter A. Habitz

IBM: 78 patents #884 of 70,183Top 2%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
📍 South Burlington, VT: #18 of 1,136 inventorsTop 2%
🗺 Vermont: #68 of 4,968 inventorsTop 2%
Overall (All Time): #21,748 of 4,157,543Top 1%
82
Patents All Time

Issued Patents All Time

Showing 26–50 of 82 patents

Patent #TitleCo-InventorsDate
8490040 Disposition of integrated circuits using performance sort ring oscillator and performance path testing Jeanne P. Bickford, Vikram Iyengar, David E. Lackey, Jinjun Xiong 2013-07-16
8468483 Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +4 more 2013-06-18
8458632 Efficient slack projection for truncated distributions Eric A. Foreman, James C. Gregerson, Jeffrey G. Hemmett, Debjit Sinha, Natesan Venkateswaran +3 more 2013-06-04
8448110 Method to reduce delay variation by sensitivity cancellation Eric A. Foreman, Gustavo E. Tellez 2013-05-21
8413095 Statistical single library including on chip variation for rapid timing and power analysis John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett, Amol A. Joshi, Christopher J. Kiegle +2 more 2013-04-02
8239810 Method and system for optimizing a device with current source models Soroush Abbaspour, Peter Feldmann, Safar Hatami 2012-08-07
8217671 Parallel array architecture for constant current electro-migration stress testing Kanak B. Agarwal, Jerry D. Hayes, Ying Liu, Deborah M. Massey, Alvin W. Strong 2012-07-10
8141025 Method of performing timing analysis on integrated circuit chips with consideration of process variations Debjit Sinha, Eric A. Foreman, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov 2012-03-20
8141012 Timing closure on multiple selective corners in a single statistical timing run Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +4 more 2012-03-20
8141014 System and method for common history pessimism relief during static timing analysis Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala, Jeffrey P. Soreff 2012-03-20
8108816 Device history based delay variation adjustment during static timing analysis Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala, Jeffrey P. Soreff 2012-01-31
8086988 Chip design and fabrication method optimized for profit Nathan C. Buck, Howard H. Chen, James Eckhardt, Eric A. Foreman, James C. Gregerson +3 more 2011-12-27
8056035 Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +2 more 2011-11-08
7961932 Method and apparatus for manufacturing diamond shaped chips Robert J. Allen, John M. Cohn, Scott Whitney Gould, Juergen Koehl, Gustavo E. Tellez +2 more 2011-06-14
7962874 Method and system for evaluating timing in an integrated circuit Eric A. Foreman, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson 2011-06-14
7886246 Methods for identifying failing timing requirements in a digital design Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Chandramouli Visweswariah 2011-02-08
7870525 Slack sensitivity to parameter variation based timing analysis Eric A. Foreman, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson 2011-01-11
7865861 Method of generating wiring routes with matching delay in the presence of process variation David J. Hathaway, Jerry D. Hayes, Anthony D. Polson 2011-01-04
7856607 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage Gary D. Grise, Vikram Iyengar, David E. Lackey, Chandramouli Visweswariah, Vladimir Zolotov 2010-12-21
7844932 Method to identify timing violations outside of manufacturing specification limits Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Chandramouli Visweswariah 2010-11-30
7823115 Method of generating wiring routes with matching delay in the presence of process variation David J. Hathaway, Jerry D. Hayes, Anthony D. Polson 2010-10-26
7797657 Parameter ordering for multi-corner static timing analysis Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Kerim Kalafala, Peihua Qi +2 more 2010-09-14
7784003 Estimation of process variation impact of slack in multi-corner path-based static timing analysis Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Kerim Kalafala, Jeffrey M. Ritzinger +1 more 2010-08-24
7750648 Method to quickly estimate inductance for timing models Eric A. Foreman, Mark R. Lasher, William J. Livingstone, Gregory M. Schaeffer 2010-07-06
7716616 Slack sensitivity to parameter variation based timing analysis Eric A. Foreman, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson 2010-05-11