Issued Patents All Time
Showing 51–75 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7684969 | Forming statistical model of independently variable parameters for timing analysis | Mark R. Lasher, William J. Livingstone | 2010-03-23 |
| 7681157 | Variable threshold system and method for multi-corner static timing analysis | Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Kerim Kalafala, Peihua Qi +2 more | 2010-03-16 |
| 7669159 | IC tiling pattern method, IC so formed and analysis method | Robert J. Allen, John M. Cohn, William C. Leipold, Ivan L. Wemple, Paul S. Zuchowski | 2010-02-23 |
| 7620921 | IC chip at-functional-speed testing with process coverage evaluation | Eric A. Foreman, Gary D. Grise, Vikram Iyengar, David E. Lackey, Chandramouli Visweswariah +2 more | 2009-11-17 |
| 7555740 | Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis | Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Kerim Kalafala, Peihua Qi +2 more | 2009-06-30 |
| 7489204 | Method and structure for chip-level testing of wire delay independent of silicon delay | Anthony D. Polson | 2009-02-10 |
| 7464359 | Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure | William J. Livingstone | 2008-12-09 |
| 7444608 | Method and system for evaluating timing in an integrated circuit | Eric A. Foreman, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson | 2008-10-28 |
| 7418689 | Method of generating wiring routes with matching delay in the presence of process variation | David J. Hathaway, Jerry D. Hayes, Anthony D. Polson | 2008-08-26 |
| 7401307 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson | 2008-07-15 |
| 7302673 | Method and system for performing shapes correction of a multi-cell reticle photomask design | David J. Hathaway, Jerry D. Hayes, Anthony D. Polson, Tad J. Wilder | 2007-11-27 |
| 7289659 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, John M. Cohn, Scott Whitney Gould, Juergen Koehl, Gustavo E. Tellez +2 more | 2007-10-30 |
| 7266474 | Ring oscillator structure and method of separating random and systematic tolerance values | Jerry D. Hayes | 2007-09-04 |
| 7181711 | Prioritizing of nets for coupled noise analysis | Eric A. Foreman, Gregory M. Schaeffer | 2007-02-20 |
| 7089143 | Method and system for evaluating timing in an integrated circuit | Eric A. Foreman, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson | 2006-08-08 |
| 7089129 | Electromigration check of signal nets using net capacitance to evaluate thermal characteristics | — | 2006-08-08 |
| 6948146 | Simplified tiling pattern method | Robert J. Allen, John M. Cohn, William C. Leipold, Ivan L. Wemple, Paul S. Zuchowski | 2005-09-20 |
| 6854099 | Balanced accuracy for extraction | Lewis W. Dewey, III, Thomas G. Mitchell | 2005-02-08 |
| 6848089 | Method and apparatus for detecting devices that can latchup | Micah Galland, Steven E. Washburn | 2005-01-25 |
| 6757876 | Method for use of hierarchy in extraction | — | 2004-06-29 |
| 6624651 | Kerf circuit for modeling of BEOL capacitances | David M. Fried | 2003-09-23 |
| 6574782 | Decoupled capacitance calculator for orthogonal wiring patterns | L. William Dewey, III, Thomas G. Mitchell | 2003-06-03 |
| 6519752 | Method of performing parasitic extraction for a multi-fingered transistor | William C. Bakker, L. William Dewey, III, Judith H. McCullen, Edward W. Seibert, Michael J. Sullivan | 2003-02-11 |
| 6490708 | Method of integrated circuit design by selection of noise tolerant gates | John M. Cohn, Scott Whitney Gould, Jose L. Neves, William F. Smith, Larry Wissel +1 more | 2002-12-03 |
| 6477686 | Method of calculating 3-dimensional fringe characteristics using specially formed extension shapes | L. William Dewey, III | 2002-11-05 |