Issued Patents All Time
Showing 76–82 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6473887 | Inclusion of global wires in capacitance extraction | L. William Dewey, III, Edward W. Seibert | 2002-10-29 |
| 6460167 | Efficient system for multi-level shape interactions | L. William Dewey, III | 2002-10-01 |
| 6430729 | Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing | L. William Dewey, III, Judith H. McCullen, Edward W. Seibert | 2002-08-06 |
| 6185722 | Three dimensional track-based parasitic extraction | Laura R. Darden, James Engel, William J. Livingstone, Daniel Joseph Mainiero, Jeannie H. Panner +2 more | 2001-02-06 |
| 5761080 | Method and apparatus for modeling capacitance in an integrated circuit | William DeCamp, John J. Ellis-Monaghan, Edward W. Seibert | 1998-06-02 |
| 5045911 | Lateral PNP transistor and method for forming same | Chang-Ming Hsieh, Yi-Shiou Huang | 1991-09-03 |
| 4996164 | Method for forming lateral PNP transistor | Chang-Ming Hsieh, Yi-Shiou Huang | 1991-02-26 |