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Data processing system to implement wiring/silicon blockages via parameterized cells |
Christopher J. Berry, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean James Salisbury +1 more |
2019-08-06 |
| 9858377 |
Constraint-driven pin optimization for hierarchical design convergence |
Christopher J. Berry, Randall J. Darden, Joseph J. Palumbo, Shyam Ramji, Sourav Saha +2 more |
2018-01-02 |
| 8010922 |
Automated method for buffering in a VLSI design |
Frank Malgioglio, Brian A. Lasseter, Joseph J. Palumbo |
2011-08-30 |
| 7568176 |
Method, system, and computer program product for hierarchical integrated circuit repartitioning |
Robert M. Averill, III, Joseph J. Palumbo |
2009-07-28 |
| 6629298 |
Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design |
Peter J. Camporese, Leon Sigal, Patrick M. Williams |
2003-09-30 |
