Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8635393 | Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type | Wolfgang Anton Spirkl | 2014-01-21 |
| 7499371 | Semiconductor memory system with a variable and settable preamble f | — | 2009-03-03 |
| 7467254 | Semiconductor memory device with write protected memory banks | — | 2008-12-16 |
| 7092300 | Memory apparatus having a short word line cycle time and method for operating a memory apparatus | Wolfgang Anton Spirkl | 2006-08-15 |
| 7047371 | Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory | — | 2006-05-16 |
| 7009902 | Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a normal mode and a refresh mode | — | 2006-03-07 |
| 6922764 | Memory, processor system and method for performing write operations on a memory region | Robert Feurle, Paul Schmölz, Andreas Täuber | 2005-07-26 |
| 6791358 | Circuit configuration with signal lines for serially transmitting a plurality of bit groups | Andreas Jakobs | 2004-09-14 |
| 6781220 | Printed circuit board for semiconductor memory device | Andreas Täube, Paul Schmölz, Robert Feurle | 2004-08-24 |
| 6707705 | Integrated dynamic memory device and method for operating an integrated dynamic memory | Paul Schmölz, Robert Feurle, Andreas Täuber | 2004-03-16 |
| 6646908 | Integrated memory chip with a dynamic memory | Andreas Täuber, Robert Feurle, Paul Schmölz | 2003-11-11 |
| 6628553 | Data output interface, in particular for semiconductor memories | Robert Feurle, Paul Schmölz, Andreas Täuber | 2003-09-30 |
| 6252443 | Delay element using a delay locked loop | Albert M. Chu, Frank D. Ferraiolo | 2001-06-26 |
| 6229364 | Frequency range trimming for a delay line | Albert M. Chu, Christopher Miller | 2001-05-08 |
| 6127866 | Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays | Albert M. Chu, John A. Fifield, Jason Rotella | 2000-10-03 |
| 6100733 | Clock latency compensation circuit for DDR timing | Albert M. Chu | 2000-08-08 |
| 6043694 | Lock arrangement for a calibrated DLL in DDR SDRAM applications | — | 2000-03-28 |
| 5978931 | Variable domain redundancy replacement configuration for a memory device | Toshiaki Kirihata, Garbiel Daniel, Karl-Peter Pfefferl | 1999-11-02 |
| 5881003 | Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration | Toshiaki Kirihata, Garbiel Daniel, Karl-Peter Pfefferl | 1999-03-09 |
| 4965464 | Power amplifier circuit for integrated digital circuits | Paul-Werner von Basse, Andrea Herlitzek, Dieter Kohlert, Ulrich Schaper | 1990-10-23 |
| 4958319 | Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs | Paul-Werner von Basse, Andrea Herlitzek, Dieter Kohlert, Ulrich Schaper | 1990-09-18 |
| 4612560 | Field effect transistor operating in the enhancement mode | Erhard Kohn | 1986-09-16 |